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  1 of 230 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information a bout device errata, click here: www.maxim - ic.com/errata . general description the ds3170 combines a ds3/e3 framer and an liu (single - chip transceiver) to interface to a ds3/e3 physical copper line. applications access concentrators multiservice access platforms (msaps) routers and switches s onet/sdh adm multiservice protocol platform (mspps) sonet/sdh muxes pbxs test equipment pdh multiplexer/ demultiplexer digital cross connect integrated - access device (iad) ordering information part temp range pin - package ds3170 0c to +70c 100 csbga ds3170+ 0c to +70c 100 csbga ds3170n - 40c to +85c 100 csbga ds3170n+ - 40 c to +85c 100 csbga +denotes a lead (pb) - free/rohs compliant package. functional diagram ds3170 ds3/e3 line ds3/ e3 liu ds3/e3 framer/ formatter system backplane features ? single - chip transceiver for ds3 and e3 ? performs receive clock/data recovery and transmit waveshaping for ds3 and e3 ? jitter a ttenuator can be placed either in the receive or transmit path ? interfaces to 75 ? coaxial cable at lengths up to 380 meters or 1246 feet (ds3), or 440 meters or 1443 feet (e3) ? uses 1:2 transformers on both tx and rx ? on - chip ds3 (m23 or c- bit) and e3 (g.751 or g.832) framer ? built - in hdlc controller with 256 - byte fifo for the insertion/extraction of ds3 pmdl, g.751 sn bit, and g.832 nr/gc bytes ? on - chip bert for prbs and repetitive pattern generation, detection and analysis ? large performance - monitoring counte rs for accumulation intervals of at least 1 second ? flexible overhead insertion/extraction port for ds3, e3 framers ? loopbacks include line, diagnostic, framer, payload, and analog with capabilities to insert ais in the directions away from loopback directio ns ? integrated clock rate adapter to generate the remaining internally required 44.736mhz (ds3) and 34.368mhz (e3) from a single - clock reference source ? clad reference clock can be 44.736mhz, 34.368mhz, 77.76mhz, 51.84mhz, or 19.44mhz ? software compatible wi th ds3171 ? ds3174 sct product family ? 8 - /16- bit parallel and slave spi serial ( 10mbps) microprocessor interface ? low - power (0.5w) 3.3v operation (5v tolerant i/o) ? 100- pin small 11mm x 11mm (1mm) csbga ? industrial temperature operation: - 40c to +85c ? ieee 1 149.1 jtag test port product brief ds3170 ds3/e3 single - chip transceiver 19 - 5785; rev 2; 3/11
ds3170 ds3/e3 single - chip transceiver 2 of 230 table of contents 1 detailed description 10 2 block diagrams 10 3 applications 12 4 feature details 13 4.1 g lobal f eatures .................................................................................................................................. 13 4.2 r eceive ds3/e3 liu f eatures .............................................................................................................. 13 4.3 j itter a ttenuator f eatures ................................................................................................................ 13 4.4 r eceive ds3/e3 f ramer f eatures ....................................................................................................... 13 4.5 t ransmit ds3/e3 f ormatter f eatures ................................................................................................ 14 4.6 t ransmit ds3/e3 liu f eatures ............................................................................................................ 14 4.7 c lock r ate a dapter f eatures ............................................................................................................. 14 4.8 hdlc c ontroller f eatures ................................................................................................................ 14 4.9 feac c ontroller f eatures ................................................................................................................ 14 4.10 t rail t race b uffer f eatures .............................................................................................................. 15 4.11 b it e rror -r ate t ester (bert) f eatures ............................................................................................ 15 4.12 l oopback f eatures .............................................................................................................................. 15 4.13 m icroprocessor i nterface f eatures ................................................................................................. 15 4.14 s lave s erial p eripheral i nterface (spi) f eatures ............................................................................. 15 4.15 t est f eatures ...................................................................................................................................... 15 5 standards compliance 16 6 acronyms and glossar y 17 7 major operational mo des 18 7.1 ds3/e3 f ramed liu m ode ..................................................................................................................... 18 7.2 ds3/e3 u nframed liu m ode ................................................................................................................. 20 7.3 ds3/e3 f ramed pos/neg m ode ........................................................................................................... 21 7.4 ds3/e3 u nframed pos/neg m ode ...................................................................................................... 22 7.5 ds3/e3 f ramed uni m ode .................................................................................................................... 23 7.6 ds3/e3 u nframed uni m ode ................................................................................................................ 24 8 p in descriptions 25 8.1 s hort p in d escriptions ........................................................................................................................ 25 8.2 d etailed p in d escriptions .................................................................................................................... 27 8.3 p in f unctional t iming ........................................................................................................................... 37 8.3.1 line io ............................................................................................................................................ 37 8.3.2 ds3/e3 framing overhead functional timing ................................................................................. 40 8.3.3 ds3/e3 serial data interface .......................................................................................................... 41 8.3.4 microprocessor interface functional timing .................................................................................... 43 8.3.5 jtag functional timing .................................................................................................................. 50 9 initialization and c onfiguration 51 9.1 m onitoring and d ebugging .................................................................................................................. 52 10 functional descripti on 53 10.1 p rocessor b us i nterface .................................................................................................................... 53 10.1.1 spi seria l port mode ....................................................................................................................... 53 10.1.2 8/16 bit bus widths ......................................................................................................................... 53 10.1.3 ready signal ( rdy ) ........................................................................................................................ 53 10.1.4 byte swap modes ........................................................................................................................... 53 10.1.5 read- write/data strobe modes ....................................................................................................... 53 10.1.6 clear on read/clear on write modes .............................................................................................. 53 10.1.7 interrupt and pin modes .................................................................................................................. 54 10.1.8 interrupt structure ........................................................................................................................... 54 10.2 c lo cks .................................................................................................................................................. 55 10.2.1 line clock modes ........................................................................................................................... 55 10.2.2 sources of clock output pin signals ............................................................................................... 57
ds3170 ds3/e3 single - chip transceiver 3 of 230 10.2.3 line io pin timing source selection ............................................................................................... 59 10.2.4 clock structures on signal io pins ................................................................................................. 62 10.2.5 gapped clocks ............................................................................................................................... 63 10.3 r eset and p ow er -d own ....................................................................................................................... 63 10.4 g lobal r esources ............................................................................................................................... 66 10.4.1 clock rate adapter (clad) ............................................................................................................ 66 10.4.2 8 khz reference generation ........................................................................................................... 66 10.4.3 one second reference generation ................................................................................................. 67 10.4.4 general - purpose io pins ................................................................................................................ 68 10.4.5 performance monitor counter update details ................................................................................. 69 10.4.6 transmit manual error insertion ...................................................................................................... 70 10.5 p ort r esources ................................................................................................................................... 71 10.5.1 loopbacks ...................................................................................................................................... 71 10.5.2 loss of signal propagation ............................................................................................................. 73 10.5.3 ais logic ........................................................................................................................................ 73 10.5.4 loop timing mode .......................................................................................................................... 75 10.5.5 hdlc overhead controller ............................................................................................................. 75 10.5.6 trail trace ...................................................................................................................................... 75 10.5.7 bert .............................................................................................................................................. 75 10.5.8 system port pins ............................................................................................................................ 76 10.5.9 framing modes ............................................................................................................................... 77 10.5.10 line interface mo des ....................................................................................................................... 77 10.6 ds3/e3 f ramer / f ormatter ................................................................................................................. 79 10.6.1 general description ........................................................................................................................ 79 10.6.2 features ......................................................................................................................................... 79 10.6.3 transmit formatter ......................................................................................................................... 80 10.6.4 receive framer .............................................................................................................................. 80 10.6.5 c - bit ds3 framer/formatter ............................................................................................................ 84 10.6.6 m23 ds3 framer/formatter ............................................................................................................ 87 10.6.7 g.751 e3 framer/formatter ............................................................................................................ 89 10.6.8 g.832 e3 framer/formatter ............................................................................................................ 91 10.7 hdlc o verhead c ontroller ............................................................................................................... 96 10.7.1 general description ........................................................................................................................ 96 10.7.2 features ......................................................................................................................................... 97 10.7.3 transmit fifo ................................................................................................................................. 97 10.7.4 transmit hdlc overhead processor .............................................................................................. 98 10.7.5 receive hdlc overhead processor ............................................................................................... 98 10.7.6 receive fifo .................................................................................................................................. 99 10.8 t rail t race c ontroller ....................................................................................................................... 99 10.8.1 general description ........................................................................................................................ 99 10.8.2 featur es ....................................................................................................................................... 100 10.8.3 functional description ................................................................................................................... 100 10.8.4 transmit data storage .................................................................................................................. 101 10.8.5 transmit trace id processor ......................................................................................................... 101 10.8.6 transmit trail trace processing .................................................................................................... 101 10.8.7 receive trace id processor .......................................................................................................... 101 10.8.8 receive trail trace processing ..................................................................................................... 101 10.8.9 receive data storage ................................................................................................................... 102 10.9 feac c ontroller .............................................................................................................................. 102 10.9.1 general description ...................................................................................................................... 102 10.9.2 features ....................................................................................................................................... 103 10.9.3 functional description ................................................................................................................... 103 10.10 l ine e ncoder /d ecoder ....................................................................................................................... 104 10.10.1 general description ...................................................................................................................... 104 10.10.2 features ....................................................................................................................................... 105 10.10.3 b3zs/hdb3 encoder .................................................................................................................... 105 10.10.4 transmit lin e interface ................................................................................................................. 105 10.10.5 receive line interface .................................................................................................................. 106 10.10.6 b3zs/hdb3 decoder .................................................................................................................... 106
ds3170 ds3/e3 single - chip transceiver 4 of 230 10.11 bert .................................................................................................................................................. 108 10.11.1 general description ...................................................................................................................... 108 10.11.2 features ....................................................................................................................................... 108 10.11.3 configuration and monitoring ........................................................................................................ 108 10.11.4 receive pattern detection ............................................................................................................. 109 10.11.5 transmit pattern gen eration ......................................................................................................... 111 10.12 liu ? l ine i nterface u nit .................................................................................................................... 112 10.12.1 general description ...................................................................................................................... 112 10.12.2 features ....................................................................................................................................... 112 10.12.3 detailed description ...................................................................................................................... 112 10.12.4 transmitter ................................................................................................................................... 113 10.12.5 receiver ....................................................................................................................................... 114 11 overall register map 117 12 register maps and de scriptions 119 12.1 r egisters b it m aps ............................................................................................................................ 119 12.1.1 global register bit map ................................................................................................................ 119 12.1.2 hdlc register bit map ................................................................................................................. 121 12.1.3 t3 register bit map ...................................................................................................................... 123 12.1.4 e3 g.751 register bit map ............................................................................................................ 124 12.1.5 e3 g.832 register bit map ............................................................................................................ 125 12.2 g lobal r egisters ............................................................................................................................... 126 12.2.1 register bit descriptions ............................................................................................................... 126 12.3 p ort r egister .................................................................................................................................... 133 12.3.1 register bit descriptions ............................................................................................................... 133 12.4 bert .................................................................................................................................................. 144 12.4.1 bert register map ...................................................................................................................... 144 12.4.2 bert register bit descriptions ..................................................................................................... 144 12.5 b3zs/hdb3 l ine e ncoder /d ecoder ................................................................................................... 151 12.5.1 transmit side line encoder/decoder register map ...................................................................... 151 12.5.2 receive side line encoder/decoder register map ....................................................................... 152 12.6 hdlc .................................................................................................................................................. 156 12.6.1 hdlc transmit side register map ................................................................................................ 156 12.6.2 hdlc receive side register map ................................................................................................ 159 12.7 feac c ontroller .............................................................................................................................. 163 12.7.1 feac transmit side register map ................................................................................................ 163 12.7.2 feac receive side register map ................................................................................................. 165 12.8 t rail t race ......................................................................................................................................... 168 12.8.1 trail trace transmit side .............................................................................................................. 168 12.8.2 trail trace receive side register map ......................................................................................... 169 12.9 ds3/e3 framer ................................................................................................................................... 174 12.9.1 transmit ds3 ................................................................................................................................ 174 12.9.2 receive ds3 register map ........................................................................................................... 176 12.9.3 transmit g.751 e3 ........................................................................................................................ 183 12.9.4 receive g.751 e3 register map ................................................................................................... 186 12.9.5 transmit g.832 e3 register map .................................................................................................. 191 12.9.6 receive g.832 e3 register map ................................................................................................... 194 13 jtag information 202 13.1 jtag d escription ............................................................................................................................... 202 13.2 jtag tap c ontroller s tate m achine d escription .......................................................................... 203 13.3 jtag i nstruction r egister and i nstructions ................................................................................... 205 13.4 jtag id c odes ................................................................................................................................... 206 13.5 jtag f unctional t iming ..................................................................................................................... 207 13.6 io p ins ................................................................................................................................................ 207 14 pin configurations 208 15 dc electrical charac teristics 211 16 ac tim ing characteristics 213
ds3170 ds3/e3 single - chip transceiver 5 of 230 16.1 f ramer d ata p ath ac c haracteristics ............................................................................................. 215 16.2 o verhead p ort ac c haracteristics .................................................................................................. 216 16.3 m icro i nterface ac c haracteristics ................................................................................................ 217 16.3.1 spi bus mode ............................................................................................................................... 217 16.3.2 parall el bus mode ......................................................................................................................... 219 16.4 clad j itter c haracteristics ............................................................................................................ 222 16.5 liu i nterface ac c haracteristics ..................................................................................................... 222 16.5.1 waveform templates .................................................................................................................... 222 16.5.2 liu input/output characteristics .................................................................................................... 225 16.6 jtag i nterface ac c haracteristics ................................................................................................. 227 17 package information 228 18 thermal information 229 19 revision history 230
ds3170 ds3/e3 single - chip transceiver 6 of 230 list of figures figure 2 - 1. liu external connections for the ds3/e3 port of ds3170 .................................................................. 10 figure 2 - 2. block diagram ................................................................................................................................... 11 figure 3 - 1. ds3/e3 line card .............................................................................................................................. 12 figure 7 -1 . ds3/e3 framed liu mode ................................................................................................................. 19 figure 7 -2 . ds3/e3 unframed liu mode .............................................................................................................. 20 figure 7 -3 . ds3/e3 framed pos/neg mode ....................................................................................................... 21 figure 7 -4 . ds3/e3 unframed pos/neg mode ................................................................................................... 22 figure 7 -5 . ds3/e3 framed uni mode ................................................................................................................. 23 figure 7 -6 . ds3/e3 unframed uni mode ............................................................................................................. 24 figure 8 - 1. tx line io b3zs functional timing diagram ...................................................................................... 37 figure 8 - 2. tx line io hdb3 functional timing diagram ..................................................................................... 38 figure 8 - 3. rx line io b3zs functional timing diagram ...................................................................................... 38 figure 8 - 4. rx line io hdb3 functional timing diagram ..................................................................................... 39 figure 8 - 5. tx line io uni functional timin g diagram ......................................................................................... 39 figure 8 - 6. rx line io uni functional timing diagram ........................................................................................ 40 figure 8 - 7. ds3 framing receive overhead port timing ..................................................................................... 40 f igure 8 - 8. e3 g.751 framing receive overhead port timing ............................................................................. 40 figure 8 - 9. e3 g.832 framing receive overhead port timing ............................................................................. 40 figure 8 - 10. ds3 framing transmit overhead port timing .................................................................................. 41 figure 8 - 11. e3 g.751 framing transmit overhead port timing .......................................................................... 41 figure 8 - 12. e3 g.832 framing transmit overhead port timing .......................................................................... 41 figure 8 - 13. ds3 framed mode transmit serial interface pin timing ................................................................... 42 figure 8 - 14. e3 g.751 framed mode transmit serial int erface pin timing ........................................................... 42 figure 8 - 15. e3 g.832 framed mode transmit serial interface pin timing ........................................................... 42 figure 8 - 16. ds3 framed mode receive serial interface pin timing .................................................................... 43 figure 8 - 17. e3 g.751 framed mode receive serial interface pin timing ............................................................ 43 figure 8 - 18. e3 g .832 framed mode receive serial interface pin timing ............................................................ 43 figure 8 - 19. spi serial port access for read mode, spi_cpol=0, spi_cpha = 0 ............................................ 44 figure 8 - 20. spi serial port access for read mode, spi_cpol = 1, spi_cpha = 0 .......................................... 44 figure 8 - 21. spi serial port access for read mode, spi_cpol = 0, spi_cpha = 1 .......................................... 44 figure 8 -22 . spi serial port access for read mode, spi_cpol = 1, spi_cpha = 1 .......................................... 44 figure 8 - 23. spi serial port access for write mode, spi_cpo l = 0, spi_cpha = 0 ........................................... 45 figure 8 - 24. spi serial port access for write mode, spi_cpol = 1, spi_cpha = 0 ........................................... 45 figure 8 - 25. spi serial port access for write mode, spi_cpol = 0, spi_cpha = 1 ........................................... 45 figure 8 - 26. spi serial port access for write mode, spi_cpol = 1, spi_cpha = 1 ........................................... 45 figure 8 - 27. 16- bit mode write ............................................................................................................................ 46 figure 8 - 28. 16- bit mode read ............................................................................................................................ 46 figure 8 - 29. 8- bit mode write .............................................................................................................................. 47 figure 8 - 30. 8- bit mode read .............................................................................................................................. 47 figure 8 - 31. 16- bit mode without byte swap ........................................................................................................ 48 figure 8 - 32. 16- bit mode with byte swap ............................................................................................................. 48 figure 8 - 33. clear status latched register on read ............................................................................................ 49 fig ure 8 - 34. clear status latched register on write ............................................................................................ 49 figure 8 - 35. rdy signal functional timing write ................................................................................................. 50 figure 8 - 36. rdy signal functional timing read ................................................................................................. 50 figure 10 - 1. interrupt structure ............................................................................................................................ 55 figure 10 - 2. internal tx clock .............................................................................................................................. 58 figure 10 - 3. internal r x clock .............................................................................................................................. 59 figure 10 - 4. example io pin clock muxing .......................................................................................................... 63 figure 10 - 5. reset sources ................................................................................................................................. 64 figure 10 - 6. 8kref logic .................................................................................................................................... 67 figure 10 - 7. performance moni tor update logic .................................................................................................. 70 figure 10 - 8. transmit error insert logic ............................................................................................................... 71 figure 10 - 9. loopback modes .............................................................................................................................. 72 figure 10 - 10. alb mux ........................................................................................................................................ 72 figure 10 - 11. ais signal flow .............................................................................................................................. 74 figure 10 - 12. framer detailed block diagram ...................................................................................................... 79
ds3170 ds3/e3 single - chip transceiver 7 of 230 figure 10 -13. ds3 frame format ........................................................................................................................ 81 figure 10 - 14. ds3 subframe framer state diagram ............................................................................................ 81 figure 10 - 15. ds3 multiframe framer state diagram ........................................................................................... 82 figure 10 - 16. g.751 e3 frame format ................................................................................................................. 89 figure 10 - 17. g.8 32 e3 frame format ................................................................................................................. 92 figure 10 - 18. ma byte format ............................................................................................................................. 92 figure 10 - 19. hdlc controller block diagram ..................................................................................................... 97 figure 10 - 20. trail trace controller block diagram ............................................................................................ 100 figure 10 - 21. trail trace byte (dt = trail trace data) ....................................................................................... 102 figure 10 - 22. feac controller block diagram ................................................................................................... 103 figure 10 - 23. feac codeword format .............................................................................................................. 104 figure 10 - 24. line encoder/decoder block diagram .......................................................................................... 105 figure 10 - 25. b3zs signatures .......................................................................................................................... 107 figure 10 - 26. hdb3 signatures ......................................................................................................................... 107 figure 10 - 27. bert block diagram ................................................................................................................... 108 figure 10 - 28. prbs synchronization state diagram .......................................................................................... 110 figure 10 - 29. repetitive pattern synchronization state diagram ........................................................................ 111 figure 10 -30. liu functional diagram ................................................................................................................ 112 figure 10 - 31. ds3/e3 liu block diagram .......................................................................................................... 113 figure 10 - 32. receiver jitter tolerance .............................................................................................................. 116 figure 13 - 1. jtag block diagram ...................................................................................................................... 202 figure 13 - 2. jtag tap controller state machine .............................................................................................. 203 figure 13 - 3. jtag functional timing ................................................................................................................. 207 figure 14 - 1. ds3170 pin assignments ?100- ball csbga (top view) ................................................................ 210 figure 16 - 1. clock period and duty cycle definitions ......................................................................................... 213 figure 16 - 2. rise time, fall time, and jitter definitions ..................................................................................... 213 figure 16 - 3. hold, setup, and delay definitions (rising clock edge) .................................................................. 213 figure 16 - 4. hold, setup, and delay definitions (falling clock edge) ................................................................. 214 figure 16 - 5. to/from hi z delay definitions (rising clock edge) ....................................................................... 2 14 figure 16 - 6. to/from hi z delay definitions (falling clock edge) ...................................................................... 214 figure 16 - 7. spi interface timing diagram ......................................................................................................... 218 figure 16 - 8. micro interface nonmultiplexed read/write cycle .......................................................................... 220 figure 16 - 9. micro interface multiplexed read cycle .......................................................................................... 221 f igure 16 - 10. ds3 pulse mask template ........................................................................................................... 223 figure 16 - 11. e3 waveform template ................................................................................................................ 224
ds3170 ds3/e3 single - chip transceiver 8 of 230 list of tables table 5 - 1. standards compliance ........................................................................................................................ 16 table 8 - 1. ds3170 short pin descriptions ........................................................................................................... 25 table 8 - 2. detailed pin descriptions .................................................................................................................... 27 table 9 - 1. configuration of port register settings ................................................................................................ 52 table 10 - 1. liu enable table .............................................................................................................................. 57 table 10 - 2. all possi ble clock sources based on mode and loopback ................................................................ 57 table 10 - 3. source selection of tlclk clock signal ........................................................................................... 58 table 10 - 4. source selecti on of tclko (internal tx clock) ................................................................................. 59 table 10 - 5. source selection of rclko clock signal (internal rx clock) ............................................................ 59 table 10 - 6. transmi t line interface signal pin valid timing source select ........................................................... 60 table 10 - 7. transmit framer pin signal timing source select ............................................................................. 61 table 1 0 - 8. receive line interface pin signal timing source select .................................................................... 61 table 10 - 9. receive framer pin signal timing source select .............................................................................. 62 tab le 10 - 10. reset and power - down sources ..................................................................................................... 65 table 10 - 11. clad clock source settings ........................................................................................................... 66 table 10 - 12. global 8 khz reference source table ............................................................................................. 67 table 10 - 13. port 8 khz reference source table ................................................................................................. 67 table 10 - 14. gpio global signals ....................................................................................................................... 68 table 10 - 15. gpio pin global mode select bits ................................................................................................... 68 table 10 - 16. gpio port alarm monitor select ...................................................................................................... 69 t able 10 - 17. loopback mode selections .............................................................................................................. 71 table 10 -18. line ais enable modes ................................................................................................................... 75 table 10 - 19. payload (downstream) ais enable modes ...................................................................................... 75 table 10 - 20. tsofi input pin functions .............................................................................................................. 76 table 10 - 21. tsofo/tden/output pin functions ................................................................................................ 76 table 10 - 22 tclko/tgclk output pin functions ............................................................................................... 76 table 10 - 23. rsofo/rden output pin functions ............................................................................................... 77 ta ble 10 - 24. rclko/rgclk output pin functions ............................................................................................. 77 table 10 - 25. framing mode select bits fm[2:0] ................................................................................................... 77 table 10 - 26. line mode select bi ts lm[2:0] ......................................................................................................... 78 table 10 - 27. c- bit ds3 frame overhead bit definitions ....................................................................................... 85 table 10 - 28. m23 ds3 frame overhead bit definitions ....................................................................................... 87 table 10 - 29. g.832 e3 frame overhead bit definitions ....................................................................................... 92 table 10 - 30. payload label match status ............................................................................................................ 96 table 10 - 31. pseudo- random pattern generation ............................................................................................. 109 table 10 - 32. repetitive pattern generation ........................................................................................................ 109 table 10 - 33. transformer characteristics ........................................................................................................... 114 table 10 - 34. recommended transformers ........................................................................................................ 115 table 11 - 1. register address map ..................................................................................................................... 117 table 12 - 1. global register bit map ................................................................................................................... 119 table 12 - 2. port register bit map ...................................................................................................................... 119 table 12 - 3. bert register bit map ................................................................................................................... 120 table 12 - 4. line register bit map ..................................................................................................................... 121 table 12 - 5. hdlc register bit map ................................................................................................................... 121 table 12 - 6. feac register bit map ................................................................................................................... 122 table 12 - 7. trail trace register bit map ............................................................................................................ 123 table 12 - 8. t3 register bit map ......................................................................................................................... 123 table 12 - 9. e3 g.751 register bit map .............................................................................................................. 124 table 12 - 10. e3 g.832 register b it map ............................................................................................................ 125 table 12 - 11. global register map ...................................................................................................................... 126 table 12 - 12. port register map ......................................................................................................................... 133 table 12 - 13. bert register map ...................................................................................................................... 144 table 12 - 14. transmit side b3zs/hdb3 line encoder/decoder register map ................................................... 151 table 12 - 15. receive side b3zs/hdb3 line encoder/decoder register map .................................................... 152 table 12 - 16. transmit side hdlc register map ................................................................................................ 156 tabl e 12- 17. receive side hdlc register map ................................................................................................. 159 table 12 - 18. feac transmit side register map ................................................................................................ 163
ds3170 ds3/e3 single - chip transceiver 9 of 230 table 12 - 19. feac receive side regi ster map ................................................................................................. 165 table 12 - 20. transmit side trail trace register map ......................................................................................... 168 table 12 - 21. trail trace receive side register map .......................................................................................... 169 table 12 - 22. transmit ds3 framer register map .............................................................................................. 174 table 12 - 23. receive ds3 framer register map ............................................................................................... 176 table 12 - 24. transmit g.751 e3 framer register map ...................................................................................... 183 table 12 - 25. receive g.751 e3 framer register map ....................................................................................... 186 table 12 - 26. transmit g.832 e3 framer register map ...................................................................................... 191 table 12 - 27. receive g.832 e3 framer register map ....................................................................................... 194 table 1 3 - 1. jtag instruction codes .................................................................................................................. 205 table 13 - 2. jtag id codes ............................................................................................................................... 206 table 14 - 1. ds3170 pin assignments for 100- ball csbga (sorted by s ignal name) ......................................... 208 table 14 - 2. ds3170 pin assignments for 100- ball csbga (sorted by ball #) .................................................... 209 table 15 - 1. recommended dc operatin g conditions ........................................................................................ 211 table 15 - 2. dc electrical characteristics ........................................................................................................... 211 table 15 - 3. output pin drive .............................................................................................................................. 212 table 16 - 1. framer interface timing .................................................................................................................. 215 table 16 - 2. system port interface timing ........................................................................................................... 215 table 16 -3. misc timing ..................................................................................................................................... 216 table 16 - 4. overhead port timing ..................................................................................................................... 216 table 16 - 5. spi bus mode timing ...................................................................................................................... 217 table 16 - 6. micro interface timing ..................................................................................................................... 219 table 16 - 7. ds3 waveform template ................................................................................................................ 222 table 16 - 8. ds3 waveform test parameters and limits .................................................................................... 222 table 16 - 9. e3 waveform test parameters and limits ....................................................................................... 223 table 16 - 10. receiver input characteristic s ? ds3 mode ................................................................................... 225 table 16 - 11. receiver input characteristics ? e3 mode ...................................................................................... 225 table 16 - 12. transmitter output characteristics ? ds3 modes ........................................................................... 226 table 16 - 13. transmitter output characteristics ? e3 mode ............................................................................... 226 table 16 - 14. jtag interface timing ................................................................................................................... 227 table 18 - 1. thermal information ........................................................................................................................ 229
ds3170 ds3/e3 single - chip transceiver 10 of 230 1 detailed description the ds3170 is a software - configured, ds3/e3, single- chip transceiver (sct). the line interface unit (liu) has independent rece ive and transmit paths. the receiver liu block performs clock and data recovery from a b3zs - or hdb3 - coded ami signal and monitors for loss of the incoming signal, and can be bypassed for direct clock and data input. the receiver liu block optionally perfo rms b3zs/hdb3 decoding. the transmitter liu drives standard pulse - shape waveforms onto 75? coaxial cable and can be bypassed for direct clock and data output. the jitter attenuator can be put in the transmit or receive data path when the liu is enabled. bu ilt - in ds3/e3 framers transmit and receive data in properly formatted c - bit ds3, m23 ds3, g.751 e3 or g.832 e3 data streams. functions not used are powered down to reduce system power requirements. the ds3170 conforms to the telecommunications standards li sted in table 5 -1 . 2 block diagrams figure 2 -1 shows the external components required at the liu interface for proper operation. figure 2 -2 shows the functional block diagram of the one channel ds3/e3 sct. figure 2 - 1 . liu external connections for the ds3/e3 port of ds3170 1:2ct 1:2ct transmit receive txp txn rxp rxn 0.01uf 3.3v power plane ground plane vdd ds3/e3 liu interface 0.1uf 1uf 330 ? (1%) 330 ? (1%) 0.01uf 0.1uf 1uf 0.01uf 0.1uf 1uf vdd vdd vss vss vss
ds3170 ds3/e3 single - chip transceiver 11 of 230 figure 2 - 2 . block diagram tsofo/tden rlclk rxp rxn tpos/tdat tneg tlclk ds3/e3 transmit liu ieee p1149.1 jtag test access port d[15:0] a[8:1] ale cs rd / ds wr / r / w serial or parallel up inteface jtdo jtclk jtms jtdi jtrst hdlc feac txp txn llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer roh rohclk rohsof toh tohclk tohsof rser rclko/rgclk rsofo/rden ds3/e3 receive liu tais tua1 tohen clock rate adapter refclk mode int gpio[8:1] width rdy tclko/tgclk plb alb ua1 gen rpos/rdat rneg/rclv rst b3zs/ hdb3 encoder b3zs/ hdb3 decoder serial interface mode: spi (sclk, mosi, and miso) a[0]/bswap spi tclki tser tsofi tx bert rx bert ds3170
ds3170 ds3/e3 single - chip transceiver 12 of 230 3 applications ? access concentrators ? multiservice access platforms ? atm and frame relay equipment ? routers and switches ? sonet/sdh adm ? sonet/sdh muxes ? pbxs ? digital cross connect ? pdh multiplexe r/demultiplexer ? test equipment ? integrated access device (iad) figure 3 -1 show s a ds3170 application. figure 3 - 1 . ds3/e3 line card digital cross connect (dcs) t3/e3 trans - formers ds3/e3 line ds3/e 3 backplane signals t3/e3 line card (#1) t3/e3 trans - formers ds3/e3 line t3/e3 line card (#n) ds3/e3 backplane signals ds3170 ds3/e3 sct t3/e3 trans - formers t3/e3 line card (#n+1) ds3/e3 backplane singals t3/e3 trans - formers t3/e3 li ne card (#n+n) ds3170 ds3/e3 sct ds3170 ds3/e3 sct ds3170 ds3/e3 sct
ds3170 ds3/e3 single - chip transceiver 13 of 230 4 feature details the f ollowing sections describe the features provided by the ds3170 sct. 4.1 global features ? supports the following transmission formats: c - bit ds3 m23 ds3 g.751 e3 g.832 e3 ? all controls and status fields are software accessible over either an 8/16 - bit microprocess or port or a slave serial bus communication port up to 10 mbps (spi) ? on - chip clock rate adapter incorporates two separate internal plls to generate the necessary ds3 or e3 clock used internally from an input clock reference (ds3, e3, 51.84 mhz, 77.76 mhz, or 19.44 mhz) ? optional transmit loop timed clock mode using the receive clock ? optional transmit clock mode using references generated by the internal clock rate adapter (clad) ? clock, data and co ntrol signals can be inverted to allow a glueless interface to other devices ? detection of loss of transmit clock and loss of receive clock ? supports gapped 52 mhz clock rates for signals embedded in sonet/sdh ? jitter attenuator can be placed in either trans mit or receive path when the liu is enabled. ? automatic one - second, external or manual update of performance monitoring counters ? framing and line code error insertion available 4.2 receive ds3/e3 liu features ? performs equalization, gain control, and clock and d ata recovery for incoming ds3 and e3 signals ? agc/equalizer block handles from 0 db to 15 db of cable loss ? interfaces directly to a dsx - 3 monitor signal (20 db flat loss) using built - in pre - amp ? digital and analog loss of signal (los) detectors (ansi t1.231 and itu g.775) ? loss -of - lock status indication for internal phase- locked loop 4.3 jitter attenuator features ? fully integrated, requires no external components ? standards - compliant jitter attenuation/jitter transfer ? can be inserted into the receive path or the t ransmit path ? 16- bit buffer depth 4.4 receive ds3/e3 framer features ? b3zs/hdb3 decoding ? frame synchronization for m23 and c - bit parity ds3, g.751 e3 and g.832 e3 ? detection of rai, ais, ds3 idle signal, loss of signal (los), severely errored framing event (sefe ), change of frame alignment (cofa), receipt of b3zs/hdb3 codewords, ds3 application id bit, ds3 m23/c - bit format mismatch, g.751 national bit, and g.832 rdi (ferf), payload type, and timing marker bits ? detection and accumulation of bipolar violations (bpv ), code violations (cv), excessive zeroes occurrences (exz), f - bit errors, m - bit errors, fas errors, lof occurrences, p - bit parity errors, cp - bit parity errors, bip -8 errors, and far end block errors (febe) ? manual or automatic one - second update of performa nce monitoring counters ? the e3 national bit (sn) is forwarded to a status register bit, the hdlc controller or the feac controller ? hdlc controller with 256 byte fifo for ds3 path maintenance data link (pmdl), g.751 national bit, or g.832 nr or gc channels ? feac controller with four - codeword fifo for ds3 feac channel ? 16- byte trail trace buffer compares and stores g.832 trail access point identifier ? ds3 m23 c - bits configurable as payload or overhead, stored in registers for software inspection ? most framing o verhead fields presented on the receive overhead port ? framer pass - through mode for clear - channel applications and externally defined frame formats
ds3170 ds3/e3 single - chip transceiver 14 of 230 4.5 transmit ds3/e3 formatter features ? frame insertion for m23 and c - bit parity ds3, g.751 e3 and g.832 e3 ? b3zs/h db3 encoding ? formatter pass - through mode for clear channel applications and externally defined frame formats ? generation of rai, ais, ds3 idle signal, and g.832 - e3 rdi ? automatic or manual insertion of bipolar violations (bpvs), excessive zeroes (exz) occurr ences, f - bit errors, m- bit errors, fas errors, p- bit parity errors, cp - bit parity errors, bip- 8 errors, and far end block errors (febe) ? the e3 national bit (sn) can be sourced from a control register, from the hdlc controller, or from the feac controller ? m ost framing overhead fields can be sourced from transmit overhead port ? hdlc controller with 256 byte fifo for ds3 path maintenance data link (pmdl), g.751 national bit, or g.832 nr or gc channels ? feac controller for ds3 feac channel can be configured to se nd one codeword, one codeword continuously, or two different codewords back -to - back to send ds3 line loopback commands ? 16- byte trail trace buffer sources the g.832 trail access point identifier ? insertion of g.832 payload type, and timing marker bits from r egisters ? ds3 m23 c - bits configurable as payload or overhead; as overhead they can be controlled from registers or the transmit overhead port 4.6 transmit ds3/e3 liu features ? drives standards - compliant ds3 and e3 waveshapes onto 75? coaxial cable ? waveshape tem plate compliance over all cable lengths without lbo adjustment ? tri - state line driver outputs support protection switching applications ? line driver monitor circuit and alarm output ? wide 50 20% transmit clock duty cycle ? line build - out (lbo) control ? output dr iver monitor 4.7 clock rate adapter features ? generation of the internally needed ds3 (44.736 mhz) and e3 (34.368 mhz) clocks a from single input reference clock ? input reference clock can be 77.76 mhz, 51.84 mhz, 44.736mhz, 34.368 mhz, or 19.44 mhz ? internally derived clock can be used as references for liu and jitter attenuator ? derived clock can be transmitted off - chip for external system use through tclko pin ? standards - compliant jitter and wander requirements 4.8 hdlc controller features ? designed to handle multi ple lapd messages without host intervention ? 256 byte receive and transmit fifos are large enough to handle the three ds3 pmdl messages (path id, idle signal id, and test signal id) that are sent and received once per second ? handles all of the normal layer 2 tasks including zero stuffing/destuffing, fcs generation/checking, abort generation/checking, flag generation/detection, and byte alignment ? programmable high or low water marks for the transmit and receive fifos ? terminates the path maintenance data link in ds3 c - bit parity mode or the g.751 sn bit or the g.832 nr or gc channels 4.9 feac controller features ? designed to handle multiple feac codewords without host intervention ? receive feac automatically validates incoming codewords and stores them in a 4 - codewo rd fifo ? transmit feac can be configured to send one codeword, one codeword continuously, or two different codewords back -to - back to send ds3 line loopback commands ? terminates the feac channel in ds3 c - bit parity mode or the sn bit in e3 mode
ds3170 ds3/e3 single - chip transceiver 15 of 230 4.10 trail trace bu ffer features ? extraction and storage of the incoming g.832 trail access point identifier in a 16 - byte receive register ? insertion of the outgoing trail access point identifier from a 16 - byte transmit register ? receive trace identifier unstable status indicat ion 4.11 bit error - rate tester (bert) features ? generates and detects pseudo - random patterns and repetitive patterns from 1 to 32 bits in length ? supports pattern insertion/extraction in ds3/e3 payload, or entire data stream ? large 24 - bit error counter allows tes ting to proceed for long periods without host intervention ? errors can be inserted in the generated bert patterns for diagnostic purposes (single bit errors or specific bit - error rates) ? off - line monitoring on the receive bert 4.12 loopback features ? liu terminal loopback (transmit to receive) - alb ? line facility loopback (receive to transmit) with optionally transmitting unframed all - one payload toward system/trunk interface - llb ? framer diagnostic loopback (transmit to receive) with optionally transmitting unfram ed all - one signal toward line/tributary interface - dlb ? simultaneous line facility loopback (llb) and framer diagnostic loopback (dlb) ? framer payload loopback (receive to transmit) with optionally transmitting unframed all - one payload toward system/trunk i nterface - plb 4.13 microprocessor interface features ? multiplexed or nonmultiplexed 8 - or 16 - bit control port ? intel and motorola bus compatible ? global reset input pin ? global interrupt output pin ? eight programmable i/o pins (gpiox) 4.14 slave serial peripheral inter face (spi) features ? three - wire synchronous serial data link operating in full duplex slave mode up to 10 mbps ? glueless connection and fully compliant to motorola popular communication processors such as mpc8260 and microcontrollers such as m68hc11 ? software provision ability for active phase of the serial clock (i.e. rising edge versus falling edge), bit ordering of the serial data (most significant first versus least significant bit first) 4.15 test features ? five pin jtag port ? all functional pins are inout pins in jtag mode ? standard jtag instructions: sample/preload, bypass, extest, clamp, highz, idcode ? custom jtag instructions to use ram bist ? ram bist on all internal ram ? hiz pin to force all digital output and inout pins into hiz ? test pin for manufacturing scan test modes
ds3170 ds3/e3 single - chip transceiver 16 of 230 5 standards compliance table 5 - 1 . standards compliance specification specification title ansi t1.102 - 1993 digital hierarchy ? electrical interfaces t1.107 - 1995 digital hierarchy ? formats specifi cation t1.231 - 1997 digital hierarchy ? layer 1 in - service digital transmission performance monitoring t1.404 - 1994 network - to - customer installation ? ds3 metallic interface specification t1.646 -1995 broadband isdn ? physical layer specification for user - network interfaces including ds1/atm atm forum af - phy - 0034.000 e3 public uni, august, 1995 af - phy - 0054.000 ds3 physical layer interface specification, january, 1996 etsi ets 300 686 business telecommunications; 34mbps and 140mbits/s digital leased lines (d34u, d34s, d140u and d140s); network interface presentation, 1996 tbr 24 business telecommunications; 34mbit/s digital unstructured and structured lease lines; attachment requirements for terminal equipment interface , 1997 ets en 300 689 access and terminals (at); 34mbps digital leased lines (d34u and d34s); terminal equipment interface, july 2001 ets 300 689 business telecommunications (btc); 34 mbps digital leased lines (d34u and d34s), terminal equipment interface , v 1.2.1, 2001 -07 ietf rf c 2496 definition of managed objects for the ds3/e3 interface type , january, 1999 iso iso 3309:1993 information technology ? telecommunications & information exchange between systems ? high level data link control (hdlc) procedures ? frame structure , fi fth edition, 1993 itu - t g.703 physical/electrical characteristics of hierarchical digital interfaces, 1991 g.704 synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels, july, 1995 g.751 digital multiplex equi pment operating at the third order bit rate of 34,368 kbit/s and the fourth order bit rate of 139,264 kbit/s and using positive justification, 1993 g.775 loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria, novem ber, 1994 g.823 the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy , 1993 g.824 the control of jitter and wander within digital networks that are based on the 1544kbps hierarchy , 1993 g.832 transport of sdh elements on pdh networks ? frame and multiplexing structures, november, 1995 i.432 b - isdn user - network interface ? physical layer specification, march, 1993 o.151 error performance measuring equipment operating at the primary rate and above, october, 1992 q.921 isdn user - network interface ? data link layer specification , march 1993 telcordia gr -499- core transport systems generic requirements (tsgr): common requirements, issue 2, december 1998 gr - 820 - core generic digital transmission surveillance , issue 1, november 1994 ieee ieee std 1149 - 1990 ieee standard test access port and boundary - scan architecture, (includes ieee std 1149- 1993) october 21, 1993
ds3170 ds3/e3 single - chip transceiver 17 of 230 6 acronyms and glossar y definition of the terms used in this data sheet: ? ccm ? clear - channel mode ? clad ? clock rate adapter ? clear channel ? a datastream with no framing included, also known as unframed ? frm ? frame mode ? fsct ? framer single- chip transceiver mode ? hdlc? high- level data- link control ? packet ? hdlc packet ? sct ? single- chip transceiver (framer and liu) ? s ct mode? ds3/e3 framer and liu ? unchannelized ? see clear channel
ds3170 ds3/e3 single - chip transceiver 18 of 230 7 major operational mo des the major operational modes are determined by the fm[2:0] framer mode bits, as well as a few other control bits. unused features are powered down and the data paths are h eld in reset. the configuration registers of the unused features can be written to and read from. some of the io pins change functions in different operational modes. the line interface operational modes are determined by the lm[2:0] bits. 7.1 ds3/e3 framed li u mode frame mode fm[2:0] ds3 c - bit framed 000 ds3 m23 framed 001 e3 g.751 framed 010 e3 g.832 framed 011 liu mode lm[2:0] tzsd & rzsd tlen port.cr2 ja off, b3zs or hdb3 001 0 0 ja rx, b3zs or hdb3 010 0 0 ja tx, b3zs or hdb3 011 0 0 ja off, ami 001 1 0 ja rx, ami 010 1 0 ja tx, ami 011 1 0
ds3170 ds3/e3 single - chip transceiver 19 of 230 figure 7 - 1 . ds3/e3 framed liu mode tsofo/tden rlclk rxp rxn tpos/tdat tneg tlclk ds3/e3 transmit liu ieee p1149.1 jtag test access port d[15:0] a[8:1] ale cs rd / ds wr / r / w serial or parallel up inteface jtdo jtclk jtms jtdi jtrst hdlc feac txp txn llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer roh rohclk rohsof toh tohclk tohsof rser rclko/rgclk rsofo/rden ds3/e3 receive liu tais tua1 tohen clock rate adapter refclk mode int gpio[8:1] width rdy tclko/tgclk plb alb ua1 gen rpos/rdat rneg/rclv rst b3zs/ hdb3 encoder b3zs/ hdb3 decoder serial interface mode: spi (sclk, mosi, and miso) a[0]/bswap spi tclki tser tsofi tx bert rx bert
ds3170 ds3/e3 single - chip transceiver 20 of 230 7.2 ds3/e3 unframed liu mode the frame mode determines the clad clock rate, liu mode and selects b3zs or hdb3. frame mode fm[2:0] ds3 unframed 100 e3 unframed 110 liu mode lm[2:0] tzsd & rzsd tlen port.cr2 ja off, b3zs or hdb3 001 0 0 ja rx, b3zs or hdb3 010 0 0 ja tx, b3zs or hdb3 011 0 0 ja off, ami 001 1 0 ja rx, ami 010 1 0 ja tx, ami 011 1 0 figure 7 - 2 . ds3/e3 unframed liu mode tden rlclk rxp rxn tpos tneg tlclk ds3/e3 transmit liu ieee p1149.1 jtag test access port d[15:0] a[8:1] ale cs rd / ds wr / r / w serial or parallel up inteface jtdo jtclk jtms jtdi jtrst txp txn llb dlb rser rclko rden ds3/e3 receive liu tais tua1 clock rate adapter refclk mode int gpio[8:1] width rdy tclko plb alb ua1 gen rpos rneg rst b3zs/ hdb3 encoder b3zs/ hdb3 decoder serial interface mode: spi a[0]/bswap spi tclki tser tx bert rx bert (sclk, mosi, and miso)
ds3170 ds3/e3 single - chip transceiver 21 of 230 7.3 ds3/e3 framed pos/neg mode frame mode fm[2:0] ds3 c - bit framed 000 ds3 m23 framed 001 e3 g.751 framed 010 e3 g.832 framed 011 liu mode lm[2 :0] tzsd & rzsd tlen port.cr2 liu off, b3zs or hdb3 000 0 1 liu off, ami 000 1 1 figure 7 - 3 . ds3/e3 framed pos/neg mode tsofo/tden rlclk tpos tneg tlclk ieee p1149.1 jtag test access port d[15:0] a[8:1] ale cs rd / ds wr / r / w serial or parallel up inteface jtdo jtclk jtms jtdi jtrst hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer roh rohclk rohsof toh tohclk tohsof rser rclko/rgclk rsofo/rden tais tua1 tohen clock rate adapter refclk mode int gpio[8:1] width rdy tclko/tgclk plb alb ua1 gen rpos rneg rst b3zs/ hdb3 encoder b3zs/ hdb3 decoder serial interface mode: spi a[0]/bswap spi tclki tser tsofi tx bert rx bert (sclk, mosi, and miso)
ds3170 ds3/e3 single - chip transceiver 22 of 230 7.4 ds3/e3 unframed pos/neg mode the frame mode determines the clad clock rate if used as the transmit clock and selects b3zs or hdb3. frame mode fm[2:0] ds3 unframed 100 e3 unframed 110 liu mode lm[2:0] tzsd & rzsd tlen port.cr2 liu off, b3zs or hdb3 000 0 1 liu off, ami 000 1 1 figure 7 - 4 . ds3/e3 unframed pos/neg mode tden rlclk tpos tneg tlclk ieee p1149.1 jtag test access port d[15:0] a[8:1] ale cs rd / ds wr / r / w serial or parallel up inteface jtdo jtclk jtms jtdi jtrst llb dlb rser rclko rden tais tua1 clock rate adapter refclk mode int gpio[8:1] width rdy tclko plb ua1 gen rpos rneg rst b3zs/ hdb3 encoder b3zs/ hdb3 decoder serial interface mode: spi a[0]/bswap spi tclki tser tx bert rx bert alb (sclk, mosi, and miso)
ds3170 ds3/e3 single - chip transceiver 23 of 230 7.5 ds3/e3 framed uni mode frame mode fm[2:0] ds3 c - bit framed 000 ds3 m23 framed 001 e3 g.751 framed 010 e3 g.832 framed 011 liu mode lm[2:0] tzsd & rzsd tlen port.cr2 unipolar mode 1xx x 1 figure 7 - 5 . ds3/e3 framed uni mode tsofo/tden rlclk tdat tlclk ieee p1149.1 jtag test access port d[15:0] a[8:1] ale cs rd / ds wr / r / w serial or parallel up inteface jtdo jtclk jtms jtdi jtrst hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer roh rohclk rohsof toh tohclk tohsof rser rclko/rgclk rsofo/rden tais tua1 tohen clock rate adapter refclk mode int gpio[8:1] width rdy tclko/tgclk plb alb ua1 gen rdat rlcv rst serial interface mode: spi a[0]/bswap spi tclki tser tsofi tx bert rx bert (sclk, mosi, and miso)
ds3170 ds3/e3 single - chip transceiver 24 of 230 7.6 ds3/e3 unframed uni mode the frame mode determines the clad clock rate if used as the transmit clock. frame mode fm[2:0] ds3 unframe d 100 e3 unframed 110 liu mode lm[2:0] tzsd & rzsd tlen port.cr2 unipolar mode 1xx x 1 figure 7 - 6 . ds3/e3 unframed uni mode rlclk tdat tlclk ieee p1149.1 jtag test access port d[15:0] a[8:1] ale cs rd / ds wr / r / w serial or parallel up inteface jtdo jtclk jtms jtdi jtrst llb dlb rser rclko tais tua1 clock rate adapter refclk mode int gpio[8:1] width rdy tclko plb ua1 gen rdat rlcv rst serial interface mode: spi a[0]/bswap spi tclki tser tx bert rx bert alb tden rden (sclk, mosi, and miso)
ds3170 ds3/e3 single - chip transceiver 25 of 230 8 pin descriptions note: in jtag mode, all digital pins ar e bidirectional to increase the effectiveness of board level atpg patterns for isolation of interconnect failures. 8.1 short pin descriptions table 8 - 1 . ds3170 short pin descriptions ipu (input with pullup), oz ( output tri - stateable), oa (analog output), ia (analog input), io (bidirectional in/out) name pin type function line i/o tlclk b7 o transmit line clock output tpos/tdat e9 o transmit positive ami/data tneg d9 o transmit negative ami txp e1, e2 oa transmit positive analog txn f1, f2 oa transmit negative analog rlclk a8 i receive clock input rxp a4 ia receive positive analog rxn a3 ia receive negative analog rpos/rdat f10 ia positive ami/data rneg/rlcv f9 ia negative ami/line code violati on ds3/e3 overhead interface toh c7 i transmit overhead tohen e10 i transmit overhead enable tohclk d7 o transmit overhead clock tohsof g9 o transmit overhead start of frame roh b6 o receive overhead rohclk c9 o receive overhead clock rohsof f8 o receive overhead start of frame ds3/e3 serial data tclki c10 i transmit line clock input tsofi a9 i transmit start of frame input tser b10 i transmit serial data tclko/tgclk b9 o transmit clock output/gapped clock tsofo/tden c8 o transmit framer s tart of frame/data enable rser c6 o receive serial data rclko/rgclk a6 o receive/clock output/gapped clock rsofo/rden b8 o receive framer start of frame/data enable microprocessor interface d[15] g8 io data [15] d[14] h10 io data [14] d[13] h9 io data [13] d[12] h8 io data [12] d[11] j10 io data [11] d[10] j9 io data [10] d[9] g6 io data [9]
ds3170 ds3/e3 single - chip transceiver 26 of 230 name pin type function d[8] j8 io data [8] d[7]/spi_cpol k8 io data [7]/spi interface clock polarity d[6]/spi_cpha h7 io data [6]/spi interface clock phase d[5]/spi_swap j7 i o data [5:3]/spi bit order swap d[4] k7 io data [4] d[3] h6 io data [3] d[2]/spi_sclk j6 io data [2]/spi serial interface clock < 10 mhz d[1]/spi_mosi k9 io data [1] spi serial interface data master out - slave in d[0]spi_miso j5 io data [0]/spi serial interface data master in - slave out a[8:1] h5, j4, h4, k3, j3, h3, k2, j2 i address [8:1] a[0]/bswap k5 address [0]/byte swap mode ale g4 i address latch enable cs a1 i chip select (active low) rd/ds b2 i read strobe (active low) / data strobe (activ e low) wr /r/ w c2 i write strobe (active low)/r/w select rdy j1 oz ready handshake (active low) int d8 o interrupt (open drain active low) mode f3 i mode select (rd/wr or ds strobe mode) width h2 i width select (8 - or 16 - bit interface) spi c3 i spi s erial bus mode misc i/o gpio[8:0| d4, d3, g5, f6, g7, f7, e7, e8 io general - purpose io [8:1] test f5 i test enable (active low) hiz b4 i high - impedance test enable (active low) rst e6 i reset (active low) jtag jtclk a5 i jtag clock jtms b3 ipu jta g mode select (with pullup) jtdi c4 ipu jtag data input (with pullup) jtdo d5 oz jtag data output jtrst e5 ipu jtag reset (active low with pullup) clad refclk h1 i reference clock power v ss c1, k1, k6, g10, a10, a2 pwr ground, 0v potential v dd b1, d1, k4, k10, d10, a7 pwr digital 3.3v avddr c5 pwr analog 3.3v for receive liu avddt f4 pwr analog 3.3v for transmit liu
ds3170 ds3/e3 single - chip transceiver 27 of 230 name pin type function avddj e3 pwr analog 3.3v for jitter attenuator avddc g3 pwr analog 3.3v for clad avssr b5 pwr analog ground for receive liu avsst e4 pwr analog ground for transmit liu avssj d2 pwr analog ground for jitter attenuator avssc g1 pwr analog ground for clad unused unused1 d6 n/a unused unused2 g2 n/a unused 8.2 detailed pin descriptions table 8 - 2 . detailed pin descriptions ipu (input with pullup), oz (output tri - stateable), oa (analog output), ia (analog input), io (bidirectional inout) pin name type pin description line io tlclk o transmit line clock output tlclk : this signal is available when the transmit line interface pins are enabled ( port.cr2 . this output signal can be inverted. tlen). this clock is typically used as the clock reference for the tdat and tneg signals, but can also be used as the reference for the tsofi, t ser, and tsofo / tden signals. o ds3: 44.736 mhz + 20 ppm o e3: 34.368 mhz + 20 ppm tpos / tdat o transmit positive ami / data output tpos : when the port line interface is configured for b3zs, hdb3 or ami mode and the transmi t line interface pins are enabled ( port.cr2 . this output signal can be inverted. tlen), a high on this pin indicates that a positive pulse should be transmitted on the line. the signal is updated on the positive clock edge of the referenced clock pin i f the clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock. the signal is typically referenced to the tlclk line clock output pins, but it can be referenced to the tclko, tclki, rlclk or rclko pins. this output signal can be disabled when the tx liu is enabled. tdat : when the port line interface is configured for uni mode and the transmit line interface pins are enabled ( port.cr2 . this output signal can be inverted. tlen), the un - encoded transmit signal is output on this pin. the signal is updated on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock. the signal is typically reference d to the tlclk line clock output pins, but it can be referenced to the tclko, tclki, rlclk or rclko pins o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm
ds3170 ds3/e3 single - chip transceiver 28 of 230 pin name type pin description tneg o transmit negative ami / line oh mask tneg : when the port li ne is configured for b3zs, hdb3 or ami mode and the transmit line interface pins are enabled ( port.cr2 . this output signal can be inverted. tlen), a high on this pin indicates that a negative pulse should be transmitted on the line. the signal is updat ed on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock. the signal is typically referenced to the tlclk line clock output pins, but it can be referenced to the tclko, tclki, rlclk or rclko pins. o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm txp oa transmit positive analog txp : this pin and the txn pin form a differential ami output which is coupled to the outbound 75 ? co axial cable through a 2:1 step - down transformer ( figure 2 -1 ). this output is enabled when the tx liu is enabled and the output is enabled to be driven. when it is not enabled, it is in a high impedance sta te. o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm txn oa transmit negative analog txn : this pin and the txp pin form a differential ami output which is coupled to the outbound 75 ? coaxial cable through a 2:1 step - down transformer ( figure 2 -1 ). this output is enabled when the tx liu is enabled and the output is enabled to be driven. when it is not enabled, it is in a high impedance state. o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm rxp ia receive posit ive analog rxp : this pin and the rxn pin form a differential ami input which is coupled to the outbound 75 ? coaxial cable through a 2:1 step - up transformer ( figure 2 -1 ). this input is used when the rx liu is enabled and is ignored when the liu is disabled. o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm rxn ia receive negative analog rxn : this pin and the rxp pin form a differential ami input which is coupled to the outbound 75 ? coaxial cable through a 2:1 step - up transformer ( figure 2 -1 ). this input is used when the liu is enabled and is ignored when the liu is disabled. o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm rlclk i receive line clock input rlclk : this clock is typically used for the reference clock for the rpos / rdat, rneg / rlcv signals but can also be used as the reference clock for the rser, rsofo / rden, tsofi, tser, tsofo / tden, tpos / tdat and tneg signals. this input is ignored when the liu is enabled. this input signal can be inverted. o ds3: 44.736 mhz + 20 ppm o e3: 34.368 mhz + 20 ppm
ds3170 ds3/e3 single - chip transceiver 29 of 230 pin name type pin description rpos / rdat iad receive positive ami / data rpos : when the port line is configured for b3zs, hdb3 or ami mode and the liu is disabled, a high on this pin ind icates that a positive pulse has been detected using an external liu. the signal is sampled on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. the signal is typically referenced to the rlclk line clock input pins, but it can be referenced to the rclko output pins. this input signal can be inverted. rdat : when the port line interface is configured for uni mode, the un - encoded receive signal is input on thi s pin. the signal is sampled on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. the signal is typically referenced to the rlclk line clock input pins, bu t it can be referenced to the rclk output pins. this input signal can be inverted. o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm rneg / rlcv iad receive negative ami / line code violation / line oh mask input rneg : when the port line is configured for b3zs, hdb3 or ami mode and the liu is disabled, a high on this pin indicates that a negative pulse has been detected using an external liu. the signal is sampled on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted , otherwise it is sampled on the falling edge of the clock. the signal is typically referenced to the rlclk line clock input pins, but it can be referenced to the rclko output pins. this input signal can be inverted. o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbp s + 20ppm rlcv : when the port line interface is configured for uni mode, the bpv counter in the encoder/decoder block is incremented each clock when this signal is high. the signal is sampled on the positive clock edge of the referenced clock pin if the clo ck pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. the signal is typically referenced to the rlclk line clock input pins, but it can be referenced to the rclko output pins. this input signal can be inverted. ds3/e3 o verhead interface toh i transmit overhead toh : when the port framer is configured for one of the ds3 or e3 framing modes, this signal will be used to over - write the ds3 or e3 framing overhead bits when tohen is active. in t3 mode, the x - bits, p - bits, m -b its, f - bits, and c- bits are input. in g.751 e3 mode, all of the fas, rai, and national use bits are input. in g.832 e3 mode, all of the fa1, fa2, em, tr, ma, nr, and gc bytes are input. the tohsof signal marks the start of the framing bit sequence. this si gnal is sampled at the same time as the tohclk signal transitions high to low. this signal can be inverted. tohen i transmit overhead enable / start of frame input tohen : when the port framer is configured for one of the ds3 or e3 framing modes, this sign al will be used the determine which ds3 or e3 framing overhead bits to over - write with the signal on the toh pin. the tohsof signal marks the start of the framing bit sequence. this signal is sampled at the same time as the tohclk signal transitions high t o low. this signal can be inverted.
ds3170 ds3/e3 single - chip transceiver 30 of 230 pin name type pin description tohclk o transmit overhead clock tohclk : when the port framer is configured for one of the ds3 or e3 framing modes, this clock is used for the transmit overhead port signals toh, tohen and tohsof. the tohsof output sign al is updated and the toh and tohen input signals are sampled at the same time this clock signal transitions from high to low. the external logic is expected to sample tohsof signal and update the toh and tohen signals on the rising edge of this clock sign al. this clock is a low frequency clock. this signal can be inverted. tohsof o transmit overhead start of frame tohsof : when the port framer is configured for one of the ds3 or e3 framing modes, this signal is used to mark the start of a ds3 or e3 overhea d sequence on the toh pin. in t3 mode, the first x - bit is marked . in g.751 e3 mode, the first bit of the fas word is marked . in g.832 e3 mode, the first bit of the fa1 byte is marked . the sequence starts on the same high to low transition of the tohclk c lock that this signal is high. this signal is updated at the same time as the tohclk signal transitions high to low. this signal can be inverted. roh o receive overhead roh : when the port framer is configured for one of the ds3 or e3 framing modes, this s ignal outputs the value of the receive overhead bits. the rohsof signal marks the start of the framing bit sequence. in t3 mode, the x - bits, p - bits, m - bits, f- bits, and c- bits are output (note: in m23 mode, the c- bits are extracted even though they are ma rked as data at the payload interface). in g.751 e3 mode, all of the fas, rai, and national use bits are output. in g.832 e3 mode, all of the fa1, fa2, em, tr, ma, nr, and gc bytes are output. this signal is updated at the same time as the rohclk signal tr ansitions high to low. this signal can be inverted. rohclk o receive overhead clock rohclk : when the port framer is configured for one of the ds3 or e3 framing modes, this clock is used for the receive overhead port signals roh and rohsof. the rohsof and roh output signals are updated at the same time this clock signal transitions from high to low. the external logic is expected to sample rohsof and roh signal on the rising edge of this clock signal. this clock is a low frequency clock. this signal can be inverted. rohsof o receive overhead start of frame rohsof : when the port framer is configured for one of the ds3 or e3 framing modes this signal is used to mark the start of a ds3 or e3 overhead sequence on the roh pins. in t3 mode, the first x - bit is mar ked . in g.751 e3 mode, the first bit of the fas word is marked . in g.832 e3 mode, the first bit of the fa1 byte is marked. the sequence starts on the same high to low transition of the rohclk clock that this signal is high. this signal is updated at the sa me time as the rohclk signal transitions high to low. this signal can be inverted. ds3/e3 serial data overhead interface tclki i transmit line clock input tclki : this clock is typically used for the reference clock for the tsofi, tser, and tsofo / tden s ignals but can also be used as the reference for the tpos / tdat and tneg signals. this clock is not used when the part is in loop time mode or the clad clocks are used as the transmit clock source. ( port.cr3 .cladc) this input signal can be inverted. o ds3: 44.736 mhz + 20 ppm o e3: 34.368 mhz + 20 ppm
ds3170 ds3/e3 single - chip transceiver 31 of 230 pin name type pin description tsofi i transmit start of frame input see table 10-20 . tsofi : this signal can be used to align the start of the ds3 or e3 frames on the tser pin to an external signal. in framed modes, the tsofi signal can be used to align the start of frame signal position on the tser/toh pin to the rising edge of a signal on this pin. the signal edge does not need to occur on every frame and can be tied high or low. the signa l is sampled on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. the signal is typically referenced to the tclki transmit clock input pins, but it can be referenced to the tlclk, tclko, rclko and rlclk clock pins. this signal can be inverted. tser i transmit serial data tser : when the port framer is configured for either the ds3 or e3 framed modes, this pin is used as the source of the ds3/e3 payload data . when the port is configured for a clear channel mode, this pin is used as the source of the ds3/e3 data signal. the signal is sampled on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. the signal is typically referenced to the tclki transmit clock input pins, but it can be referenced to the tlclk, tclko / tgclk, rclko and rlclk clock pins this signal can be inverted. o ds3: 44.736 mbps + 20ppm o e3: 34.368 m bps + 20ppm tclko / tgclk o transmit clock output / gapped clock see table 10-22 . tclko : when tclko is selected by port.cr3 .tclks, this clock output is enabled. t his clock is the same clock as the internal framer transmit clock. this clock is typically used for the reference clock for the tsofi, tser, and tsofo / tden signals but can also be used as the reference for the tpos / tdat and tneg signals. this signal ca n be inverted. o ds3: 44.736 mhz + 20 ppm o e3: 34.368 mhz + 20 ppm tgclk : when tgclk is selected by port.cr3 .tclks, this gated output clock is enabled. this gapped clock is the same clock as the internal framer transmit clock and is gated by tden. this clock is typically used for the reference clock for the tser signal. this signal can be inverted.
ds3170 ds3/e3 single - chip transceiver 32 of 230 pin name type pin description tsofo / tden o framer start of frame / data enable see table 10-21 . tso fo : when the port framer is configured for the ds3 or e3 framed modes and the tsofo pin function is selected, this signal is used to indicate the start of the ds3/e3 frame on the tser pin. this signal pulses high three clocks before the first overhead bit in a ds3 or e3 frame that will be input on tser. the signal is updated on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock. the signal is typically refere nced to the tclki transmit clock input pins, but it can be referenced to the tlclk, tclko, rclko and rlclk clock pins. this signal can be inverted. tden : when the port framer is configured for the ds3 or e3 framed modes and the tden pin function is selecte d, this signal is used to mark the ds3/e3 frame bits on the tser pin. the signal goes high three clocks before the start of ds3/e3 payload bits and goes low three clocks before the end of the ds3/e3 payload bits. the signal is updated on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock. the signal is typically referenced to the tclki transmit clock input pins, but it can be referenced to the tlclk, tclko, rc lko and rlclk clock pins. this signal can be inverted. rser o receive serial data rser : when the port framer is configured for the ds3 or e3 framed modes, this pin outputs the receive data signal from the liu or receive line pins. the signal is updated o n the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock. the signal is typically referenced to the rclko receive clock output pin, but it can be referenced to t he rgclk and rlclk clock pins. this signal can be inverted o ds3: 44.736 mbps + 20ppm o e3: 34.368 mbps + 20ppm rclko / rgclk o receive clock output / gapped clock see table 10-24 . rclko : when the port frame r is configured for the ds3 or e3 framed modes and rclko is selected, this clock output signal is active. it is the same as the internal receive framer clock. this clock is typically used for the reference clock for the rser, rsofo / rden signals but can a lso be used as the reference for the rpos / rdat, rneg / rlcv, tsofi, tser, tsofo / tden, tpos / tdat and tneg signals. this signal can be inverted. o ds3: 44.736 mhz + 20 ppm o e3: 34.368 mhz + 20 ppm rgclk : when the port is configured for ds3/e3 framed mode a nd rgclk is selected, this gated clock output signal is active. it is the same as the internal receive framer clock gated by rden. this clock is typically used for the reference clock for the rser. this signal can be inverted rsofo / rden o receive frame r start of frame /data enable see table 10-23 . rsofo : when the port framer is configured for the ds3 or e3 framed modes and the rsofo pin function is enabled, this signal is used to indicate the start of the ds3/e3 frame. this signal indicates the first ds3/e3 overhead bit on the rser pin when high. the signal is updated on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling e dge of the clock. the signal is typically referenced to the rclko receive clock output pin, but it can be referenced to the rlclk clock input pin. this signal can be inverted. rden : when the port framer is configured for the ds3 or e3 framed modes and the rden pin function is enabled, this signal is used to indicate the ds3/e3 payload bit
ds3170 ds3/e3 single - chip transceiver 33 of 230 pin name type pin description positions of the data on the rser pin. the signal goes high during each ds3/e3 payload bit and goes low during each ds3/e3 overhead bit. the signal is updated on the posit ive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock. the signal is typically referenced to the rclko receive clock output pin, but it can be referenced to the rlclk cl ock input pin. this signal can be inverted. microprocessor interface d[15:8] io upper 8 bits of the bi - directional 16 or 8 bit data bus d[15:8] : upper bits of the 16 - bit or 8 - bit data bus used to input data during register writes, and data outputs during register reads. the upper 8 bits are not used in 8 bit bus mode. not driven when cs =1 or rst =0. d[7]/ spi_cpol io bit 7 of bi - directional data bus / spi bus clock polarity d[7] : bit 7 of the 16 - bit or 8- bit data bus used to input data during register wri tes, and data outputs during register reads. not driven when cs =1 or rst =0. spi_cpol: this signal selects the clock polarity when spi = 1. see section 8.3.4.1 for detailed timing and functionality informat ion. default setting is low. d[6]/ spi_cpha io bit 6 of bi - directional data bus / spi bus clock phase d[6] : bit 6 of the 16 - bit or 8- bit data bus used to input data during register writes, and data outputs during register reads. not driven when cs =1 or rst =0. spi_cpha: this signal selects the clock phase when spi = 1. see section 8.3.4.1 for detailed timing and functionality information. default setting is low. d[5]/ spi_swap io bit 5 of bi - directional data bus / spi bit order swap d[5] : bit 5 of the 16 - bit or 8- bit data bus used to input data during register writes, and data outputs during register reads. not driven when cs =1 or rst =0. spi_swap : this signal is active when spi=1. the address and data bi t order is swapped when spi_swap is high. the r/w and b bit positions are never changed in the control word. 0 = msb is transmitted and received first. 1 = lsb is transmitted and received first. d[4:3] io bits 4,3 of bi - directional data bus d[4:3] : bits 3 ,4 of the 16 - bit or 8 - bit data bus used to input data during register writes, and data outputs during register reads. not driven when cs =1 or rst =0. d[2]/ spi_sclk io bit 2 of bi - directional data bus / spi serial clock input < 10 mhz d[2] : bit 2 of the 16 - bit or 8- bit data bus used to input data during register writes, and data outputs during register reads. not driven when cs =1 or rst =0. spi_sclk: spi serial clock input when spi = 1. d[1]/ spi_mosi io bit 1 of bi - directional data bus / spi serial bus mas ter - out slave - in d[1] : bit 1 of the 16 - bit or 8- bit data bus used to input data during register writes, and data outputs during register reads. not driven when cs =1 or rst =0. spi_mosi: spi serial data input (master - out slave - in) when spi = 1. d[0]/ spi_mi so io bit 0 of bi - directional data bus / spi serial bus master - in slave - out d[0] : bit 0 of the 16 - bit or 8- bit data bus used to input data during register writes, and data outputs during register reads. not driven when cs =1 or rst =0. spi_miso: spi serial d ata output (master - in slave - out) when spi = 1. a[8:1] i address bus (minus lsb) / device address [8:1] a[8:1] : identifies the specific 16 bit registers, or group of 8 bit registers, being accessed. a[0] / bswap address bus lsb / byte swap / device ad dress [0] a[0] : this signal is connected to the lower address bit in 8 bit systems. (width=0) 1 = output register bits 15:8 on d[7:0], d[15:8] not driven 0 = output register bits 7:0 on d[7:0], d[15:8] not driven bswap : this signal is tied high or low in 1 6 bit systems. (width=1) 1 = output register bits 15:8 on d[7:0], 7:0 on d[15:8] 0 = output register bits 7:0 on d[7:0], 15:8 on d[15:8] ale i address latch enable ale : this signal is used to latch the address on the a[10:0] pins in multiplexed
ds3170 ds3/e3 single - chip transceiver 34 of 230 pin name type pin description address sy stems. when it is high the address is fed through the address latch to the internal logic. when it transitions to low, the address is latched and held internally until the signal goes back high. ale should be tied high for nonmultiplexed address systems. cs i chip select (active low) cs : this signal must be low during all accesses to the registers rd / ds i read strobe (active low) / data strobe (active low) rd : read strobe mode (mode=0): rd is low during a register read. ds : data strobe mode (mode=1): ds is low during either a register read or a write. wr / r/ w i write strobe (active low) / r/w select wr : write strobe mode (mode=0): wr is low during a register write. r/ w : data strobe mode (mode=1): r/ w is high during a register read cycle, and low during a register write cycle. rdy oz ready handshake (active low) rdy : this ready signal is driven low when the current read or write cycle can progress. when the current read or write cycle is not ready it is driven high. when device is not selected it is not driven. not driven when rst =0 or cs =1. int oz interrupt (active low) int : this interrupt signal is driven low when an event is detected on any of the enabled interrupt sources in any of the register banks. when there are no active and enabled interrupt sources, the pin can be programmed to either drive high or not drive high. the reset default is to not drive high when there are no active and enabled interrupt source. all interrupt sources are disabled when rst =0 and they must be programmed t o be enabled. not driven when rst =0. mode i mode select rd / wr or ds strobe mode mode : 1 = data strobe mode, 0 = read/write strobe mode width i data bus width select 8 or 16 - bit interface width : 1 = 16 - bits, 0 = 8 bits spi i spi serial bus mode select s pi : 1 = spi serial bus mode, 0 = parallel bus mode misc i/o gpio1 io general purpose io 1 gpio1 : this signal is configured to be a general purpose io pin, or an alarm output signal. gpio2 io general purpose io 2 gpio2 : this signal is configured to be a general purpose io pin, or the 8krefo output signal, or an alarm output signal. gpio3 io general purpose io 3 gpio3 : this signal is configured to be a general purpose io pin. gpio4 io general purpose io 4 gpio4 : this signal is configured to be a general purpose io pin, or the 8krefi input signal. when configured for 8krefi mode the signal frequency should be 8,000 hz +/ - 500 ppm and about 50% duty cycle. gpio5 io general purpose io 5 gpio5 : this signal is configured to be a general purpose io pin, or an alarm output signal. gpio6 io general purpose io 6 gpio6 : this signal is configured to be a general purpose io pin, or the tmei input signal. when configured for tmei input, the signal low time and high time must be greater than 500 nsec. gpio7 io gene ral purpose io 7
ds3170 ds3/e3 single - chip transceiver 35 of 230 pin name type pin description gpio7 : this signal is configured to be a general purpose io pin. gpio8 io general purpose io 8 gpio8 : this signal is configured to be a general purpose io pin, or the pmu input signal. when configured for pmu input, the signal low time a nd high time must be greater than 500 nsec. test i test enable (active low) test : this signal enables the internal scan test mode when low. for normal operation tie high. this is an asynchronous input. hiz i high impedance test enable (active low) hiz : t his signal puts all digital output and bi - directional pins in the high impedance state when it low and jtrst is low. for normal operation tie high. this is an asynchronous input. rst i reset (active low) rst : this signal resets all the internal processor registers and logic when low. this pin should be low while power is applied and set high after the power is stable. this is an asynchronous input. jtag jtclk i jtag clock jtclk : this clock input is typically a low frequency (less than 10 mhz) 50% duty cycle clock signal. jtms ipu jtag mode select (with pullup) jtms : this input signal is used to control the jtag controller state machine and is sampled on the rising edge of jtclk. jtdi ipu jtag data input (with pullup) jtdi : this input signal is used t o input data into the register that is enabled by the jtag controller state machine and is sampled on the rising edge of jtclk. jtdo oz jtag data output jtdo : this output signal is the output of an internal scan shift register enabled by the jtag controll er state machine and is updated on the falling edge of jtclk. the pin is in the high impedance mode when a register is not selected or when the jtrst signal is high. the pin goes into and exits the high impedance mode after the falling edge of jtclk jtrst ipu jtag reset (active low with pullup) jtrst : this input forces the jtag controller logic into the reset state and forces the jtdo pin into high impedance when low. this pin should be low while power is applied and set high after the power is stable. t he pin can be driven high or low for normal operation, but must be high for jtag operation. clad refclk i reference clock clki : this pin must have a clock which is either 44.736 mhz, 34.368 mhz, 77.76 mhz, 51.84 mhz or 19.44 mhz +/ - 20 ppm and transmissi on quality jitter and wander. no io pins have a timing relationship to this pin. power vss pwr ground, 0 volt potential common to digital core, digital io and all analog circuits vdd pwr digital 3.3v common to digital core and digital io avddr pwr ana log 3.3v for receive liu powers receive liu avddt pwr analog 3.3v for transmit liu powers transmit liu avddj pwr analog 3.3v for jitter attenuator powers jitter attenuator avddc pwr analog 3.3v for clad powers clock rate adapter
ds3170 ds3/e3 single - chip transceiver 36 of 230 pin name type pin description avssr pwr analog g round for receive liu avsst pwr analog ground for transmit liu avssj pwr analog ground for jitter attenuator avssc pwr analog ground for clad
ds3170 ds3/e3 single - chip transceiver 37 of 230 8.3 pin functional timing 8.3.1 line io 8.3.1.1 b3zs/hdb3/ami mode transmit pin functional timing there is no suggested time a lignment between the txp, txn and tx line signals and the tlclk clock signal. the tx data signal is not a readily available signal, it is meant to represent the data value of the other signals. the txp and txn signals are only available when the line is i n b3zs/hdb3 or ami mode and the liu is enabled. the tpos, tneg and tlclk signals are only available when the line is in b3zs/hdb3 or ami mode and the transmit line pins are enabled. the tpos, tneg and tlclk pins can be enabled at the same as the liu is ena bled. the tpos and tneg signals change a small delay after the positive edge of the reference clock if the clock pin is not inverted, otherwise they change after the negative edge. the tlclk clock pin is the clock reference typically used for the tpos and tneg signals, but they can be time referenced to the tclki, tclko, rlclk or rclko clock pins. the tpos and tneg pins can be inverted, but the polarity of txp and txn can not be inverted. txp and txn are differential analog output pins. they are biased aro und ? vdd and pulse above and below the bias voltage by about 1 volt. these signals are connected to the windings of a 1:2 step down transformer and the other winding of the transformer creates the tx line signal. the tx line signal is a bipolar signal tha t pulses about 1 volt positive and 1 volt negative above and below ground (0 volts). see figure 2 -1 for a diagram of the external connections. figure 8 -1 and figure 8 -2 show the relationship between the analog and the digital outputs. figure 8 - 1 . tx line io b3zs functional timing diagram tlclk tpos tneg (tx data) b3zs codeword (tx line) + - txp txn v v b b b v b v 0 v bias v
ds3170 ds3/e3 single - chip transceiver 38 of 230 figure 8 - 2 . tx line io hdb3 functional timing diagram tlclk tpos tneg (tx data) hdb3 codeword (tx line) + - txp txn v v b b b v b v 0 v bias v 8.3.1.2 b3zs/hdb3/ami mode receive pin functional timing there is no suggested time alignment between the rxp, rxn and rx line signals and the rlclk clock signal. the rx data sign al is not an always readily available signal, it is meant to represent the data value of the other signals. the signal on rser in framed mode will be the same as the rx data signal except delayed. the rxp and rxn pins are only available when the line is i n b3zs/hdb3 or ami mode and the liu is enabled. the rpos, rneg and rlclk pins are only available when the line is in b3zs/hdb3 or ami mode and the liu is disabled. the rpos and rneg signals are sampled at the rising edge of the reference clock signal if t he clock pin is not inverted, otherwise they are sampled at the negative edge. the rlclk clock pin is the clock reference used for the rpos and rneg signals. the rpos and rneg pins can be inverted. rxp and rxn are differential analog input pins. they are b iased around ? vdd and pulse above and below the bias voltage by about 1 volt with zero cable length. these signals are connected to the windings of a 1:2 step up transformer and the other winding of the transformer is connected to the rx line signal. the rx line signal is a bipolar signal that pulses about 1 volt positive and 1 volt negative above and below ground (0 volts) with zero cable length. see figure 2 -1 for a diagram of the external connections. figure 8 -3 and figure 8 -4 show the relationship between the analog and the digital outputs. figure 8 - 3 . r x line io b3zs functional timing diagram rlclk rpos rneg (rx data) b3zs codeword (rx line) + - rxp rxn v v b b b v b v 0 v bias v
ds3170 ds3/e3 single - chip transceiver 39 of 230 figure 8 - 4 . rx line io hdb3 functional timing diagram rlclk rpos rneg (rx data) hdb3 codeword (rx line) + - rxp rxn v v b b b v b v 0 v bias v 8.3.1.3 uni mode transmit pin functional timing the tdat pin is available when the line interface is in the uni mode and the transmit line pins are enabled the tdat signal changes a small delay after the positive edge of the reference clock signal if the clock pin is not inverted, other wise they change after the negative edge. the tlclk clock pin is the clock reference typically used for the tdat signal, but the tdat can be time referenced to the tclki, tclko, rlclk or rclko clock pins. the tdat pin can be inverted. please refer to figure 8 -5 . figure 8 - 5 . tx line io uni functional timing diagram 8.3.1.4 uni mode receive pin functional timing the rdat pin is available when the line interface is in the uni mode. the rlcv pin is available when the line interface is in the uni mode . all bits on the rdat pin, will come out the rser pin, if the rser pin is enabled. the signal on the rlcv pin enables the bpv counter, which is in the line interface, to increment each clock it is high. the rdat and rlcv signals are sampled at the rising edge of the reference clock signal if the clock pin is not inverted, otherwise they are sampled at the negative edge. the rlclk clock pin is the clock reference used for the rdat and rlcv signals. the rdat and rlcv pins can be inverted. please refer to figure 8 -6 . tlclk tdat
ds3170 ds3/e3 single - chip transceiver 40 of 230 figure 8 - 6 . rx line io uni functional timing diagram rlclk rdat rlvc inc bpv counter twice inc bpv counter once 8.3.2 ds3/e3 framing overhead functional timing figure 8 -7 shows the relationship between the ds3 receive overhead port pins. figure 8 - 7 . ds3 framing receive overhead port timing roh rohsof rohclk n a fas 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 15 fas 2 fas 3 fas 1 fas 6 fas 5 fas 4 fas 7 fas 8 fas 10 a fas 9 fas 2 fas 1 n fas 3 fas 4 fas 6 fas 8 fas 5 fas 10 fas 9 figure 8 -8 shows the relationship between the e3 g.751 receive overhead port pins. figure 8 - 8 . e3 g.751 framing receive overhead port timing roh rohsof rohcl k n a fas 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 15 fas 2 fas 3 fas 1 fas 6 fas 5 fas 4 fas 7 fas 8 fas 10 a fas 9 fas 2 fas 1 n fas 3 fas 4 fas 6 fas 8 fas 5 fas 10 fas 9 figure 8 -9 shows the relationship b etween the e3 g.832 receive overhead port pins. figure 8 - 9 . e3 g.832 framing receive overhead port timing roh rohsof rohcl k gc 8 gc 7 gc 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 15 fa1 2 fa1 3 fa1 1 fa1 6 fa1 5 fa1 4 fa1 7 fa1 8 fa2 2 fa2 3 fa2 1 fa2 6 fa2 5 fa2 4 fa2 7 fa2 8 em 2 em 3 em 1 em 5 em 4
ds3170 ds3/e3 single - chip transceiver 41 of 230 figure 8 -10 shows the relationship between the d s3 transmit overhead port pins. figure 8 - 10 . ds3 framing transmit overhead port timing toh tohsof tohclk f74 c73 f73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 15 f11 x1 f13 c12 f12 c13 f14 f21 c21 x2 f23 c22 f22 c23 f24 f31 c31 p1 c32 f32 t ohen c11 figure 8 -11 shows the relationship between the e3 g.751 transmit ov erhead port pins. figure 8 - 11 . e3 g.751 framing transmit overhead port timing toh tohsof tohclk n a fas 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 15 fas 2 fas 3 fas 1 fas 6 fas 5 fas 4 fas 7 fas 8 fas 10 a fas 9 fas 2 fas 1 n fas 3 fas 4 fas 6 fas 8 fas 5 fas 9 fas 9 t ohen figure 8 -12 shows the relationship between the e3 g.832 transmit overhead po rt pins. figure 8 - 12 . e3 g.832 framing transmit overhead port timing toh tohclk gc 8 gc 7 gc 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 15 fa1 2 fa1 3 fa1 1 fa1 6 fa1 5 fa1 4 fa1 7 fa1 8 fa2 2 fa2 3 fa2 1 fa2 6 fa2 5 fa2 4 fa2 7 fa2 8 em 2 em 3 em 1 em 5 em 4 tohsof t ohen 8.3.3 ds3/e3 serial data interface 8.3.3.1 ds3/e3 framed mode transmit serial interface pin functional timing the tser pin is used to input ds3 or e3 p ayload data bits in all framing modes as well as the c - bits, which can be treated as payload, in ds3 m23 and e3 g.751 framing modes. the tden signal is used to determine the ds3 or e3 payload bit positions on tser. the tden signal goes high three clocks be fore the first bit of a payload sequence is clocked into the tser pin and it goes low three clocks before the payload sequence is stopped being clocked in to the tser pin. the tsofo signal pulses high three clocks before the start of the ds3 or e3 overhead bit position on tser. the tsofi pin is used to set the ds3 or e3 frame position. when the tsofi pin transitions low to high, the first ds3/e3 overhead bit position on tser will be forced to align to it figure 8 -13 to figure 8 -15 show the relationship between the transmit serial interface pins.
ds3170 ds3/e3 single - chip transceiver 42 of 230 figure 8 - 13 . ds3 framed mode transmit serial interface pin timin g tclko or tclki ds3 tser ds3 t den tsofo ds3 tgclk tsofi t ser dat a is ov erwrit t en wit h oh 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 figure 8 - 14 . e3 g.751 framed mode transmit serial interface pin timing e3 t ser e3 t den e3 tgclk tclko or tclki tsofo tsofi t ser dat a is ov erwrit t en wit h oh 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 figure 8 - 15 . e3 g.832 framed mode transmit serial interface pin timing e3 t ser e3 t den e3 tgclk tclko or tclki tsofo t ser dat a is ov erwrit t en wit h oh tsofi 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 16 17 18 19 20 8.3.3.2 ds3/e3 fra med mode receive serial interface pin functional timing the rser signal has the ds3 or e3 payload as well as the ds3 or e3 overhead bits. the rden signal is used to enable external logic for payload processing and will be high during the ds3 or e3 payload bits and low during the ds3 or e3 overhead bits. the rgclk signal can also be used to clock only the ds3 or e3 payload bits into external logic since the clock is stopped during the ds3 or e3 overhead bits. the rsofo signal marks the first overhead bit of the ds3 or e3 frame. figure 8 -16 to figure 8 -18 show the relationship between the receive serial interface pins.
ds3170 ds3/e3 single - chip transceiver 43 of 230 figure 8 - 16 . ds3 framed mode receive serial interface pin timing rcl ko o r rcl ki ds3 rser ds3 rden rsofo ds3 rgcl k x1 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 figure 8 - 17 . e3 g.751 framed mode receive serial interface pin timing e3 rser e3 rden a e3 rgc l k n fas 1111010000 rcl ko o r rcl ki rsofo 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 figure 8 - 18. e3 g.832 framed mode receive serial interface pin timing e3 rser e3 rden e3 rgc l k fa1 11110110 rcl ko o r rcl ki rsof fa2 00101000 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 16 17 18 19 20 8.3.4 microprocessor interface functional timing 8.3.4.1 spi functional timing diagrams note: the transmit and receive order of the address and data bits are selected by the d[5]/spi_swap pin. the r/w (read/wr ite) msb bit and b (burst) lsb bit position is not effected by the d[5]/spi_swap pin setting. 8.3.4.1.1 spi transmission format and cpha polarity when cpha = 0, cs may be de - asserted between accesses. an access is defined as one or two control bytes followed by a da ta byte. cs cannot be de - asserted between the control bytes, or between the last control byte and the data byte. when cpha = 0, cs may also remain asserted between accesses. if it remains asserted and the burst bit is set, no additional control bytes are e xpected after the first control byte(s) and data are transferred. if the burst bit is set, the address will be incremented for each additional byte of data transferred until cs is de - asserted. if cs remains asserted and the burst bit is not set, a control byte(s) is expected following the data byte, and the address for the next access will be received from that. anytime cs is de - asserted, the burst access is terminated. when cpha = 1, cs may remain asserted for more than one access without being toggled h igh and then low again between accesses. if the burst bit is set, the address should increment and no additional control bytes are
ds3170 ds3/e3 single - chip transceiver 44 of 230 expected. if the burst bit is not set, each data byte will be followed by the control byte(s) for the next access. additiona lly, cs may also be de - asserted between accesses when cpha =1. in the case, any burst access is terminated, and the next byte received when cs is re - asserted will be a control byte. the following diagrams describe the functionality of the spi port for the four combinations of spi_cpol and spi_cpha. they indicate the clock edge that samples the data and the level of the clock during no - transfer events (high or low). since the spi port of the ds3170 acts as a slave device, the master device provides the clo ck. the user must configure the spi_cpol and spi_cpha pins to describe which type of clock that the master device is providing. figure 8 - 19 . spi serial port access for read mode, spi_cpol=0, spi_cpha = 0 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb sck cs* mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0 f igure 8 - 20 . spi serial port access for read mode, spi_cpol = 1, spi_cpha = 0 sck cs* 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0 figure 8 - 21 . spi serial port access for read mode, spi_cpol = 0, spi_cpha = 1 sck cs* 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0 f igure 8 - 22 . spi serial port access for read mode, spi_cpol = 1, spi_cpha = 1 sck cs* 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0
ds3170 ds3/e3 single - chip transceiver 45 of 230 figure 8 - 23 . spi serial port access for write mode, spi_cpol = 0, spi_cpha = 0 0 a13 lsb msb sck cs* mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12 a11 a10 a9 a8 a7 a6 a5 b figure 8 - 24 . spi serial port access for write mode, spi_cpol = 1, spi_cpha = 0 sck cs* 0 a13 lsb msb mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12 a11 a10 a9 a8 a7 a6 a5 b figure 8 - 25 . spi serial port access for write mode, spi_cpol = 0, spi_cpha = 1 sck cs* 0 a13 lsb msb mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12 a11 a10 a9 a8 a7 a6 a5 b figure 8 - 26 . spi serial port access for write mode, spi_cpol = 1, spi_cpha = 1 sck cs* 0 a13 lsb msb mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12 a11 a10 a9 a8 a7 a6 a5 b 8.3.4.2 parallel port interface diagrams figure 8 -27 and figure 8 -29 show examples of a 16 - bit databus and an 8- bit databus, respectively. in 16- bit mode, the a[0]/bswap signal controls whether or not to byte swap. in 8 - bit mode, the a[0]/bswap signal is used as the lsb of the address bus (a[0]). the selection of databus size is determined by the width input signal. see also section 10.1.1 .
ds3170 ds3/e3 single - chip transceiver 46 of 230 figure 8 - 27 . 16 - bit mode write 0x1234 0x2b0 d[15:0] a[10:1] rd wr cs a[0]/bswap rdy z z note: address 0x2b0 = 0x1234 figure 8 - 28 . 16 - bit mode read d[15:0] a[10:1] a[0]/bswap 0x2b0 0x1234 z z note: address 0x2b0 = 0x1234 rd wr cs rdy
ds3170 ds3/e3 single - chip transceiver 47 of 230 figure 8 - 29. 8 - bit mode write 0x34 0x12 0x2b0 0x2b0 d[7:0] a[10:1] a[0]/bswap z z z z note: address 0x2b0 = 0x34 0x2b1 = 012 rd wr cs rdy figure 8 - 30. 8 - bit mode read d[7:0] a[10:1] a[0]/bswap 0x2b0 0x34 z z 0x2b0 0x12 z z note: address 0x2b0 = 0x34 0x2b1 = 012 rd wr cs rdy figure 8 -31 and figure 8 -32 are examples of databuses without and with byte swapping enabled, respectively. when the a[0]/bswap pin is set to 0, byte swapping is disabled, and when one, byte swapping is enabled. this pin should be static and not change while operating. note: address bit a[0] is not used in 16 - bit mode. see also section 10.1.3 .
ds3170 ds3/e3 single - chip transceiver 48 of 230 figure 8 - 31 . 16 - bit mode without byte swap 0x1234 0x5678 note: address 0x2b0 = 0x1234 0x2b2 = 0x5678 0x2b0 0x2b2 d[15:0] a[10:1] a[0]/bswap z z z z rd wr cs rdy figure 8 - 32 . 16 - bit mode with byte swap 0x3412 0x7856 note: address 0x2b0 = 0x1234 0x2b2 = 0x5678 0x2b0 0x2b2 d[15:0] a[10:1] a[0]/bswap z z z z rd wr cs rdy clearing status latched registers on a read or write access is selectable via the gl.cr1 .ls bcre register bit. clearing on read clears all bits in the register, while the clear on write clears only those bits which are written with a ?1? when the user writes to the status latched register. to use the clear on read method, the user must only re ad the status latched register. all bits are set to zero after the read. figure 8 -33 shows a read of a status latched register and another read of the same register verifying the register has cleared. to use the clear on write method, the user must write the register with ones in the bit locations that he desires to clear. figure 8 -34 shows a read, a write, and then a subsequent read revealing the result s of clearing of the bits, which he wrote a ?1.? see also section 10.1.6 .
ds3170 ds3/e3 single - chip transceiver 49 of 230 figure 8 - 33 . clear status latched register on read d[15:0] a[10:1] a[0]/bswap 0x1c0 0xffff 0x1c0 0x0000 z z z z rd wr cs rdy figure 8 - 34 . clear status latched register on write d[15:0] a[10:1] a[0]/bswap 0x1c0 0xffff 0x1c0 0x5555 0x1c0 0xaaaa z z z z z z rd wr cs rdy figure 8 -35 and figure 8 -36 show exaggerated views of the ready signal to describe the difference in access times to write or read to or from various memory locations on the ds3170 device. some registers will have a faster access time than others and if needed, the user can implement the rdy signal to maximize efficiency of read and write ac cesses.
ds3170 ds3/e3 single - chip transceiver 50 of 230 figure 8 - 35. rdy signal functional timing write 0x1234 0x0078 0x2b0 0x3a4 d[15:0] a[10:1] a[0]/bswap z z z z rd wr cs rdy figure 8 - 36. rdy signal functional timing read d[15:0] a[10:1] a[0]/bswap 0x1c0 0xffff 0x3a4 0xffff z z z z rd wr cs rdy see also fig ure 16-8 and figure 16-9 . 8.3.5 jtag functional timing see section 13.5 .
ds3170 ds3/e3 single - chip transceiver 51 of 230 9 initialization and c onfiguration step 1: check device id code. before any testing can be done, the device id code, which is stored in gl.idr, shoud be checked against the device id code shown below to ensure correct device is being used. current device id codes is: o ds3170 rev 1.0: 004fh step 2: initialize the device. before configuri ng for operation, make sure the device is in a known condition with all registers set to their default value by initiating a global reset. (see section 10.3 .) a global reset can be initiated via the rst pin or b y the global reset bit ( gl.cr1 .rst). a port reset is not necessary since the global reset includes a reset of the port to its default values. step 3: clear the reset. it is necessary to clear the rst bit to begin normal operation. after clearing the rst bit, the device is configured for default mode. default mode: framer: c - bit ds3 liu: disabled step 4: clear the data path resets and the port power - down bit. the default value of the data path resets is one, which keeps the internal logic in the rese t status. the user needs to clear the following bits: gl.cr1 .rstdp = 0 port.cr1 .rstdp = 0 port.cr1 .pd = 0 step 5: configure the clad if using the liu, configure the clad (which supplies the clock to the receive liu) via the clad bits in the gl.cr2 register. note: the user must supply a ds3, e3, sts - 1, 77.76 mhz, or 19.44 mhz clock to the refclk pin. step 6: select the clock source for the transmitter. loop time (use the receive clock): set port.cr3 .loopt = 1 clad source: set port.cr3 .cladc = 0 tclki source: set port.cr3 .cladc = 1 if using the clad, properly configure the clad by setti ng the clad bits in step 7: configure the framing mode and the line mode.. gl.cr2 . port . cr2 .lm[2:0] = 011 (liu on, ja in rx side) or another setting. see port.cr2. fm[2:0] set to correct mode. see table 10-26 step 8: disable payload ais (downstream ais) and line ais table 10 -25. port . cr1 .pais[2:0] = 111 port .cr1.lais[1:0] = 11 step 9: enable the port (for non - liu modes) port . cr2 .tlen = 1
ds3170 ds3/e3 single - chip transceiver 52 of 230 table 9 - 1 . configuration of port register settings mode port.cr1 0x040 port.cr2 0x042 port.cr3 0x044 port.cr4 ds3 c - bit framed 0x046 0x2000 0000 0011 0000 0111 0x0000 0x0000 ds3 m13 framed 0x2000 0000 0011 0000 1111 0x0000 0x0000 e3.751 framed 0x2000 0000 0011 0001 0111 0x0000 0x0000 e3.823 framed 0x2000 0000 0011 0001 111x 0x0000 0x0000 note: the line mode has been configured with the liu enabled and the ja in the receive path (lm[2:0] = 011) for all modes. 9.1 monitoring and debugging to determine if the device is receiving a good signal and that the chip is correctly configured for its environment, check the following status registers. receive loss of lock ? port.sr .rlol: the clock recovery circuit of the liu was unable to rec over the clock from the incoming signal. this may indicate that the liu?s master clock does not match the frequency of the incoming signal. verify that the clad is configured to match the clock input on the refclk pin (ds3, e3, sts - 1). see table 10-11 . loss of signal ? line.rsr .los: this indicates that the liu is unable to recover the clock and data because there is no signal on the line, or that the signal is at tenuated beyond recovery. loss of frame ? t3.rsr1 .lof (or e3751.rsr1 or e3832.rsr1): this indicates that the framer was unable to synchronize to the incoming data. verify that the fm bits have been correctly config ured for the correct mode of traffic (ds3, e3 g.751, e3 g.832) other helpful techniques to utilize in diagnosing a problem include using line loopback and diagnostic loopback. these features help to isolate and identify the source of the problem. line loo pback will loop the receive input to the transmit output, eliminating the transmit side input from the equation. diagnostic loopback will loop the transmit output before the liu to the receive framer, eliminating the analog receive liu and the receive side analog circuitry. one other potential problem is the line encoding/decoding . the device needs to be configured in the same mode as the far end piece of equipment. if the far end piece of equipment is transmitting and receiving hdb3/b3zs encoded data, the ds3170 also must be configured to do the same. this is controlled by the line.tcr .tzsd and the line.rcr .rzsd bits.
ds3170 ds3/e3 single - chip transceiver 53 of 230 10 functional description 10.1 processor bus interface 10.1.1 spi serial port mode the external processor bus can be configured to operate in spi serial bus mode. see the section 8.3.4.1 for detailed timing diagrams. when spi = 1, spi bus mode is implemented using four signals: clock (clk), master - out slave- in data (mosi), master - in slave - out data (miso), and chip select ( cs ). c lock polarity and phase can be set by the d[7]/spi_cpol and d[6]/spi_cpha pins. the order of the address and data bits in the serial stream is selectable using the d[5]/spi_swap pin. the r/w bit is always first and b bit is always last in the initial con trol word and are not effected by the d[5]/spi_swap pin setting. 10.1.2 8/16 bit bus widths the external processor bus can be sized for 8 or 16 bits using the width pin. when in 8 - bit mode (width=0), the address is composed of all the address bits including a[0], the lower 8 data lines d[7:0] are used and the upper 8 data lines d[15:8] are not used and never driven during a read cycle. when in 16 - bit mode (width=1), the address bus does not include a[0] (the lsb of the address bus is not routed to the chip) and al l 16 data lines d[15:0] are used. see figure 8 -27 and figure 8 -29 for functional timing diagrams. 10.1.3 ready signal ( rdy ) the rdy signal allows the micropr ocessor to use the minimum bus cycle period for maximum efficiency. when this signal goes low, the rd or wr cycle can be terminated. see figure 8 -35 for functional timing diagrams. note: the rdy signal w ill not go active if the user attempts to read or write unused registers not assigned to any design blocks. the rdy signal will go active if the user writes or reads reserved registers or unused registers within design blocks. 10.1.4 byte swap modes the processor interface can operate in byte swap mode when the data bus is configured for 16 - bit operation. the a[0]/bswap pin is used to determine whether byte swapping is enabled. this pin should be static and not change while operating. when the a[0]/bswap pin is lo w the upper register bits reg[15:8] are mapped to the upper external data bus lines d[15:8], and the lower register bits reg[7:0] are mapped to the lower external data bus lines d[7:0]. when the a[0]/bswap pin is high the upper register bits reg[15:8] are mapped to the lower external data bus lines d[7:0], and the lower register bits reg[7:0] are mapped to the upper external data bus lines d[15:8]. see figure 8 -31 and figure 8 -32 for functional timing diagrams. 10.1.5 read - write/data strobe modes the processor interface can operate in either read - write strobe mode or data strobe mode. when mode=0 the read - write strobe mode is enabled and a negative pulse on rd p erforms a read cycle, and a negative pulse on wr performs a write cycle. when mode=1 the data strobe mode is enabled and a negative pulse on ds when r/ w is high performs a read cycle, and a negative pulse on ds when r/ w is low performs a write cycle. the r ead- write strobe mode is commonly called the ?intel? mode, and the data strobe mode is commonly called the ?motorola? mode. 10.1.6 clear on read/clear on write modes the latched status register bits can be programmed to clear on a read access or clear on a write access. the global control register bit gl.cr1 .lsbcre controls the mode that all of the latched registers are cleared. when lsbcre=0, the latched register bits will be cleared when the register is written to and the write data has the register bits to clea r set. when lsbcre=1, the latched register bits that are set will be cleared when the register is read.
ds3170 ds3/e3 single - chip transceiver 54 of 230 the clear on write mode expects the user to use the following protocol: 1. read the latched status register 2. write to the registers with the bits set that need to be cleared. this protocol is useful when multiple uncoordinated software tasks access the same latched register. each task should only clear the bits with which it is concerned; the other tasks will clear the bits with which they are concerned. th e clear on read mode is simpler since the bits that were read as being set will be cleared automatically. this method will work well in a software system where multiple tasks do not read the same latched status register. the latched status register bits in clear on read mode are carefully designed not to miss events that occur while a register is being read when the latched bit has not already been set. refer to figure 8 -33 and figure 8 -34 . 10.1.7 interrupt and pin modes the interrupt ( int ) pin is configurable to drive high or high impedance when inactive. the gl.cr1 .intm bit controls the pin configuration. if it is se t, the int pin will drive high when inactive. after a reset, the int pin will be in high impedance mode until an interrupt source is active and enabled to drive the interrupt pin. 10.1.8 interrupt structure the interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. the status bits in the global status ( gl.sr ) and global status latched register ( gl.srl ) are read to determine if the interrupt source is a global event, a global performance monitor update or whether it came from the port. if the interrupt event came from the port then the port status register ( port.sr ) and port status register latched ( port.srl ) can be read to determine if the interrupt source is a common port event like the performance monitor updat e or liu or whether it came from the ds3/e3 framers, bert, hdlc, feac or trail trace status registers. if the interrupt came from the ds3/e3 framers, bert, hdlc, feac or trail trace status registers, then those registers will need to be read to determine t he event that caused the interrupt. the source of an interrupt can be determined by reading three status registers: the global, port and block status registers. when a mode is not enabled, then interrupts from that source will not occur. for example, if e3 framing mode is enabled, an interrupt source that is defined in ds3 framing, but not in e3 framing, cannot create a new interrupt. note that when modes are changed, the latched status bits of the new mode, as well as any other mode, may get set. if the da ta path reset is set during or after the mode change, the latched status bits will be automatically cleared. if the data path reset is not used to clear the latched status bits, then the registers must be cleared by reading or writing to them based on the register clear method selected.
ds3170 ds3/e3 single - chip transceiver 55 of 230 figure 10- 1 . interrupt structure gl.isr.pisrn port.isr bit srl bit srl bit srl bit srie bit srie bit srie bit block latched status and interrupt enable registers port interrupt status register global interrupt status register and interrupt enable register gl.isrie. pisrien int port interrupts global interrupts figure 10-1 not only tells the user how to determine which event caused the interrupt, it also tells the user how to enable a particular interrupt. each block has a status register interrupt enable register which must be set in order to enable an interrupt. the next step is to unmask the interrupt at the port level. this is controlled in the global interrupt status register interrupt enable register ( gl.isrie ). now the device is ready to drive the int pin low when a particular status bit gets set. for example, in order to enable ds3 out of frame int errupts, the following registers would need to be written: register bit address value written note t3.rsrie1 . 0x12c oofie 0x0002 unmask oof interrupt gl.isrie .pisrie 0 x012 0x0010 unmask port interrupts the following status registers bits will be set upon reception of oof: register bit address value read note t3.rsrl1 . 0x128 oofl 0x0002 ds3 out of frame port.isr . 0x050 fmsr 0x0001 framer block interrupt active gl.isr .pisr 0x010 0x0010 port interrupt active 10.2 clocks 10.2.1 line clock modes 10.2.1.1 loop timing enabled when loop timing is enabled ( port.cr3 .loopt), the transmit clock source is the same as the receive clock source. the tclki pin is not used as a clock source. because loop timing is enabled, the loopback functions (llb, plb and dlb) do not cause the clock sources to switch when they are activated. the transmit and receive signal pins can be timed to a single clock reference without concern about having the clock source change during loopbacks.
ds3170 ds3/e3 single - chip transceiver 56 of 230 10.2.1.1.1 liu enabled, loop timing enabled in this mode, the receive liu sources the clock for both the receive and transmit logic. the rclko, tclko and tlclk clock output pins will be the same. the transmit or receive line payload signal pins can be timed to any of these clock. the use of the rclko pin as the timing source is suggeste d. if rclko is used as the timing source, be sure to set port.cr3 .rfts = 0 for output timing. 10.2.1.1.2 liu disabled, loop timing enabled in this mode, the rlclk pin are the source of the clock for both the receive and trans mit logic. the rclko, tclko and tlclk clock output pins will both be the same as the rlclk clock. the transmit or receive line payload signals can be timed to any of these clock pins. the use of the rlclk pin as the timing source is suggested. if rlclk is used as the timing source, be sure to set port.cr3.rfts = 1 for input timing. 10.2.1.2 loop timing disabled when loop timing is disabled, the transmit clock source can be different than the receive clock source. the loopback functions, llb, plb and dlb, will caus e the clock sources to switch when they are activated. care must be taken when selecting the clock reference for the transmit and receive signals. the most versatile clocking option has the receive line interface signals timed to rlclk, the transmit line interface signals timed to tlclk, the receive framer signals timed to rclko, and the transmit framer signals timed to tclko. this clocking arrangement works in all modes. when llb is enabled, the clock on the tlclk pin will switch to the clock from the rlc lk pin or rx liu. it is recommended that the transmit line interface signals be timed to the tlclk pins. if tlclk is used as the timing source, be sure to set port.cr3 .tlts = 0 for output timing. when plb is enabled , the tclki pin will not be used and the internal transmit clock is switched to the internal receive clock. the clock on the tclko pin will switch to the clock from the rlclk pins or rx liu. the framer input signals will be ignored while plb is enabled. it is recommended that the transmit line interface signals be timed to the tclko pins. when dlb is enabled, the internal receive clock is switched to the internal transmit clock which is sourced from the tclki pin or one of the clad clocks, and the clock on the rlclk pin or from the rx liu will not be used. the clock on the rclko pin will switch to the clock on the tclki pins or one of the clad clocks. the receive line signals from the rx liu or line interface pins will be ignored. it is recommended that the receive framer pins be timed to the rclko pin. if tclko is used as the timing source, be sure to set port.cr3 .tfts = 0 for output timing. when both dlb and llb are enabled, the tlclk clock pin are connected to eithe r the rx liu recovered clock or the rlclk clock pin, and the rclko clock pin will be connected to the tclki clock pin or one of the clad clocks. it is recommended that the transmit line signals be timed to the tlclk pin, the receive line interface signals be timed to the rlclk pin, the receive framer signals be timed to the rclko pin, and the transmit framer signals be timed to the tclko pin. 10.2.1.2.1 liu enabled - clad timing disabled ? no lb in this mode, the receive liu sources the clock for the receive logic and the tclki pin sources the clock for the transmit logic. 10.2.1.2.2 liu enabled - clad timing enabled ? no lb in this mode, the receive liu sources the clock for the receive logic and one of the clad clocks sources the clock for the transmit logic. 10.2.1.2.3 liu disabled - c lad timing disabled ? no lb in this mode, the rlclk pin source the clock for the receive logic and the tclki pin sources the clock for the transmit logic. 10.2.1.2.4 liu disabled - clad timing enabled ? no lb in this mode, the rlclk pin source the clock for the rece ive logic and one of the clad clocks sources the clock for the transmit logic.
ds3170 ds3/e3 single - chip transceiver 57 of 230 10.2.2 sources of clock output pin signals the clock output pins can be sourced from many clock sources. the clock sources are the transmit input clocks pin (tclki), the receive clock input pin (rlclk), the recovered clock in the receive liu, and the clock signals in the clock rate adapter circuit (clad). the default clock source for the receive logic is the rlclk pin if the liu is disabled; otherwise the default clock is sourced from t he rx liu clock when the rx liu is enabled. the default clock source for the transmit logic is the clad clocks. the liu is enabled based on the line mode bits(lm[2:0]) (see table 10-26 ). the bits lm[2:0], lbm[2:0], loopt and cladc are located in the port configuration registers. liuen is not a register bit; it is a variable based on the line mode bits. table 10-1 decodes the lm bits for liuen selection. t able 10- 1 . liu enable table lm[2:0] liuen liu status 000 0 disabled 001 1 enabled 010 1 enabled 011 1 enabled 1xx 0 disabled table 10-2 identifies the f ramer clock source and the line clock source depending on the mode that the device is configured. putting the device in loopback will typically mux in a different clock than the normal clock source. table 10- 2 . all possible clock sources based on mode and loopback mode loopback rx framer clock source tx framer clock source tx line clock source loop timed any rlclk or rxliu same as rx same as rx normal none rlclk or rxliu tclki or clad same as tx normal llb rlclk or rxliu tclki or clad same as rx normal plb rlclk or rxliu same as rx same as rx normal dlb same as tx tclki or clad same as tx normal llb and dlb same as tx tclki or clad rlclk or rxliun
ds3170 ds3/e3 single - chip transceiver 58 of 230 table 10-3 identifies the source of the output signal tlclk based on certain variables and register bits. table 10- 3 . source selection of tlclk clock signal signal loopt ( port. cr3 ) lbm[2:0] ( port.cr4 ) llb or plb liuen cladc ( port.cr3 ) source tlclk 1 xxx na 1 x rx liu 1 xxx na 0 x rlclk 0 010 llb 1 x rx liu 0 110 llb 1 x rx liu 0 010 llb 0 x rlclk 0 110 llb 0 x rlclk 0 011 plb 1 x rx liu 0 011 plb 0 x rlclk 0 000 no x 0 clad 0 001 no x 0 clad 0 100 no x 0 clad 0 10x no x 0 clad 0 111 no x 0 clad 0 000 no x 1 tclki 0 001 no x 1 tclki 0 100 no x 1 tclki 0 10 x no x 1 tclki 0 111 no x 1 tclki figure 10-2 shows the source of the tclko signals. figure 10- 2 . internal tx clock 0 1 0 1 clad tclki port.cr3. cladc rclko payload loopback tclko table 10-4 identifies the source of the output signal tclko based on certain variables and register bits.
ds3170 ds3/e3 single - chip transceiver 59 of 230 table 10- 4 . source selection of tclko (internal tx clock) signal loopt port.cr3 lbm[2:0] ( port.cr4 ) liuen cladc ( port.cr3 ) source tclko 1 xxx 1 x rx liu 1 xxx 0 x rlclk 0 plb (011) 1 x rx liu 0 plb (011) 0 x rlclk 0 plb disabled x 0 clad 0 plb disabled x 1 tclki figure 10-3 shows the source of the rclko signals. figure 10- 3 . internal rx clock 0 1 0 1 rx liu clock rlclk liuen tclko diagnostic loopback rclko table 10-5 identifies the source of the output signal rclko based on certain variables and register bits. table 10- 5 . source selection of rclko clock signal (intern al rx clock) signal loopt port.cr3 lbm[2:0] ( port.cr4 ) liuen cladc ( port.cr3 ) source rclko 1 xxx 1 x rx liu 1 xxx 0 x rlclk 0 d lb disabled 1 x rx liu 0 dlb disabled & alb disabled 0 x rlclk 0 dlb (1xx) x 0 clad 0 dlb (1xx) or alb (001) 0 1 tclki 0 dlb (1xx) 1 1 tclki 10.2.3 line io pin timing source selection the line io pins can use any input clock pin (rlclk or tclki) or outpu t clock pin (tlclk, rclko, or tclko) for its clock pin and meet the ac timing specifications as long as the clock signal is valid for the mode the part is in. the clock select bit for the transmit line io signal group port. cr3 .tlts selects the correct input or output clock timing.
ds3170 ds3/e3 single - chip transceiver 60 of 230 10.2.3.1 transmit line interface pins timing source selection (tpos/tdat, tneg) the transmit line interface signal pin group has the same functional timing clock source as the tlclk pin described i n table 10-3 . other clock pins can be used for the external timing. the tlclk transmit line clock output pin is always a valid output clock for external logic to use for these signals when port.cr3 .tlts=0. the transmit line timing select bit (tlts) is used to select input or output clock pin timing. when tlts=0, output clock timing is selected. when tlts=1, input clock timing is selected. if tlts is set for input cl ock timing and an output clock pin is used, or if tlts is set for output clock timing and an input clock pin is used, then the setup, hold and delay timings, as specified in table 16-1 , will not be valid. there are some combinations of tlts=1 and other modes in which there is no input clock pin available for external timing since the clock source is derived internally from the rx liu or the clad. table 10- 6 . tr ansmit line interface signal pin valid timing source select loopt lbm[2:0] liuen cladc tlts valid timing to these clock pins 1 xxx x x 0 tlclk, tclko, rclko 1 xxx 0 x 1 rlclk 1 xxx 1 x 1 no valid timing to any input clock pin 0 dlb (100) x x 0 tlcl k, tclko, rclko 0 llb (010) or plb (011) x x 0 tlclk, rclko 0 dlb & llb (110) x x 0 tlclk 0 not dlb (100), not llb (010), not plb (011) and not llb & dlb (110) x x 0 tlclk, tclko (default) 0 not llb (010) and not plb (011) and not llb & dlb (110) x 0 1 no valid timing to any input clock pin 0 not llb (010) and not plb (011) and not llb & dlb (110) x 1 1 tclki 0 llb (010) or plb (011) or dlb & llb (110) 0 x 1 rlclk 0 llb (010) or plb (011) or dlb & llb (110) 1 x 1 no valid timing to any input clock pi n 10.2.3.2 transmit framer pin timing source selection (tser, tsofi, tsofo/tden) the transmit framer signal pin group has the same functional timing clock source as the tclko pin described in table 10-4 . other clo ck pins can be used for the external timing. the tclko transmit clock output pin is always a valid output clock for external logic to use for these signals when tfts=0. the transmit framer select bit (tfts) is used to select input or output clock pin timi ng. when tfts=0, output clock timing is selected. when tfts=1, input clock timing is selected. if tfts is set for input clock timing and an output clock pin is used, or if tfts is set for output clock timing and an input clock pin is used, then the setup, hold and delay timings, as specified in table 16-1 , will not be valid. there are some combinations of tfts=1 and other modes in which there is no input clock pin available for external timing since the clo ck source is derived internally from the rx liu or the clad.
ds3170 ds3/e3 single - chip transceiver 61 of 230 table 10- 7 . transmit framer pin signal timing source select loopt lbm[2:0] liuen cladc tfts valid timing to these clock pins 1 xxx x x 0 tclko, tl clk, rclko 1 xxx 0 x 1 rlclk 1 xxx 1 x 1 no valid timing to any input clock pin 0 plb (011) or dlb (100) or alb 001) 0 x 0 tclko, tlclk, rclko 0 plb (011) or dlb (100) 1 x 0 tclko, tlclk, rclko 0 dlb & llb (110) x x 0 tclko, rclko 0 llb (010) x x 0 t clko 0 not llb, dlb or plb (00x) x x 0 tclko, tlclk 0 not plb (011) x 0 1 no valid timing to any input clock pin 0 not plb (011) x 1 1 tclki 0 plb (011) 0 x 1 rlclk 0 plb (011) 1 x 1 no valid timing to any input clock pin 10.2.3.3 receive line interface pin t iming source selection (rpos/rdat, rneg/rlcv) the receive line interface signal pin group must clocked in with the rlclk clock input pin. when the liu is enabled, the receive line interface pins are not used so there is no valid clock reference. table 10- 8 . receive line interface pin signal timing source select loopt lbm[2:0] liuen cladc valid timing to these clock pins x xxx 0 x rlclk x xxx 1 x no valid timing to any clock pin 10.2.3.4 receiver framer pin timing sou rce selection (rser, rsofo/rden) the receive framer signal pin group has the same functional timing clock source as the rclko pin described in table 10-5 . other clock pins can be used for the external tim ing. the rclko receive clock output pin is always a valid output clock for external logic to use for these signals when port.cr3 .rfts=0. the receive framer timing select bit (rfts) is used to select input or output clock pin timing. when rfts=0, output clock timing is selected. when rfts=1, input clock timing is selected. if rfts is set for input clock timing and an output clock pin is used, or if rfts is set for output clock timing and an input clock pin is used, t hen the setup, hold and delay timings, as specified in table 16-1 , will not be valid. there are some combinations of rfts=1 and other modes in which there is no input clock pin available for external timin g since the clock source is derived internally from the rx liu or the clad.
ds3170 ds3/e3 single - chip transceiver 62 of 230 table 10- 9 . receive framer pin signal timing source select loopt lbm[2:0] liuen cladc rfts valid timing to these clock pins 1 xxx x x 0 rclko, tlclk, tclko 1 xxx 0 x 1 rlclk 1 xxx 1 x 1 no valid timing to any input clock pin 0 plb (011) or dlb (100) or alb (001) 0 x 0 rclko, tlclk, tclko 0 plb (011) or dlb (100) 1 x 0 rclko, tlclk, tclko 0 dlb&llb (110) x x 0 rclko, tclko 0 llb (010) x x 0 rclko, tlclk 0 not llb, dlb or plb (00x) x x 0 rclko 0 dlb (100) or llb & dlb (110) x 0 1 no valid timing to any input clock pin 0 dlb (100) or llb & dlb (110) x 1 1 tclki 0 not dlb (100) and not llb & dlb (110) 0 x 1 rlclk 0 not dlb (100) and not llb & dlb (110) 1 x 1 no valid timing to any input clock pin 10.2.4 clock structures on signal io pins the signals on the input pins (tsofi, tser) can be used with any of the clock pins for setup/hold timing on clock input and output pins. there will b e a flop at each input whose clock is connected to the signal from the input or output clock source pins with as little delay as possible from the signal on the clock io pins. this means using the input clock signal before the delays of the internal clock tree to clock the input signals, and using the output clock signals used to drive the output clock pins to clock the input signals. the signals on the output pins (tpos/tdat, tneg, tsofo/tden, rser, rsofo/rden) can be with any of the clock sources for dela y timing. there will be a flop at each output whose clock is connected to the signal from the input or output clock source pins with as little delay as possible from the signal on the clock io pins. this means using the input clock signal before the delays of the internal clock tree to clock the input signals, and using the output clock signals used to drive the output clock pins to clock the input signals.
ds3170 ds3/e3 single - chip transceiver 63 of 230 figure 10- 4 . example io pin clock muxing q q set clr d internal signal tclki pin invert rlclk pin invert rx liu clk ds3 clk e3 clk sts-1 clk clad clocks tclko pin invert clock tree tden pin invert q q set clr d delay tfts 0 1 tser pin invert q q set clr d q q set clr d internal signal delay 0 1 tfts q q set clr d internal signal tlclk pin invert clock tree tpos pin invert q q set clr d delay tlts 0 1 q q set clr d internal signal rclko pin invert clock tree rser pin invert q q set clr d delay rfts 0 1 10.2.5 gapped cl ocks the transmit and receive output clocks can be gapped in certain configurations. see table 10-22 and table 10-24 for the configuration settings. the gapped clocks are active during ds3 or e3 framed payload bits overhead bits depending on which mode the device is configured for. in the internal ds3 or e3 frame modes, the transmit gapped clock is created by the logical or of the tclko and tden signals creating a positive or negative clock edge for each payload bit, the receive gapped clock is created by the logical or of the rclko and rden signals. when the output clock is disabled, the gapped output signal is high during clock periods if the pin is not inverted, otherwise it will be low. the gapped clocks are very useful when the data being clocked does not need to be aligned with any frame structure. the data is simply clocked one bit at a time as a continuous data stream. 10.3 reset and power - down the devi ce can be reset at a global level via the gl.cr1 . rst bit or the rst pin and at the port level via the port.cr1 . rst bit and the port can be explicitly powered down via the port.cr1 . pd bit. the jtag logic is reset using the power on reset signal from one of the lius as well as from the jtrst pin. the external rst pin and the global reset bit in the global configuration register ( gl.cr1 .rst) are combined to create an internal global reset signal. the global reset signal resets all the status and control registers on the chip, except the gl.cr1 . rst bit, to their de fault values and resets all the other flops in the global logic and port to their
ds3170 ds3/e3 single - chip transceiver 64 of 230 reset values. the processor bus output signals are also forced to be hiz when the rst pin is active (low). the global reset bit ( gl.cr1 . rst) stays set after a one is written to it, but is reset to zero when the external rst pin is active or when a zero is written to it. at the port level, the global reset signal combines with the port reset bit in the port control register ( port.cr1 . rst) to create a port reset signal. the port reset signal resets all the status and control registers on the port to their default values and resets all the other flops, except port.cr1 . rst, to their reset values. the port reset bit ( port.cr1 . rst) stays set after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it. the data pat h reset function is a little different from the ?general? reset function. the data path reset signal does not reset the control register bits, but it does reset all of the status registers, counters and flops, the ?general? reset signal resets everything i ncluding the control register bits, excluding the reset bit. all clocks are functional, being controlled by configuration bits, while data path reset is active. the liu and clad circuits will be operating normally during data path reset which allows the in ternal phase locked loops to settle as quickly as possible. the liu will be sending all zeroes (los) since data path reset will be forcing the transmit tpos and tneg to logic zero. (note: the bert data path does not get reset when port.cr1 .rstdp is active.) the global data path reset bit ( gl.cr1 . rstdp) gets set to one when the global reset signal is active. the port data path reset bit ( port.cr1 . rstdp) and the port power - down bit ( port.cr1 . pd) bit gets set to one when the port reset signal is active. these control bits will be cleared when a zero is written to them when the port reset signal is not active. the global data path reset signal is active when the global data path reset bit is set. the port data path reset signal is active when either the global data path reset bit or the port data path reset bit is set. the port power - down signal is acti ve when the port power - down bit is set. figure 10- 5 . reset sources q q set clr d q q set clr d q q set clr d q q set clr d rst pin global reset port reset global data path reset port data path reset gl.cr1 . rst gl.cr1 . rstdp port.cr1 . rst port.cr1 . rstdp note: assumes active high signals q q set clr d port power down port.cr1 . pd
ds3170 ds3/e3 single - chip transceiver 65 of 230 table 10- 10 . reset and power - down sources pin register bits internal signals rst g:rst g:rs tdp p:rst p:rstdp p:pd global reset global dp reset port reset port dp reset port power dn 0 f0 f1 f0 f1 f1 1 1 1 1 1 1 1 f1 f0 f1 f1 1 1 1 1 1 1 0 1 1 f1 f1 0 1 1 1 1 1 0 1 0 x 1 0 1 0 1 1 1 0 1 0 x 0 0 1 0 1 0 1 0 0 1 f1 f1 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 register bit states ? f0: forced to 0; f1: forced to 1; 0: set to 0; 1: set to 1; x: don?t care forced: internally controlled; set: user controlled the reset signals in the devi ce are asynchronous so they no not require a clock to put the logic into the reset state. clock signals may be needed to make the logic come out of the reset state. the power - down function disables the appropriate clocks to cause the logic to generate a mi nimum of power. it also puts the liu circuits into the power - down mode. the 8kref and onesec circuits can be powered down by disabling the 8kref source. the clad can also be powered down by disabling it. after a global reset, all of the control and status registers are set to their default values and all the other flops are reset to their reset values. the global register gl.cr1 . rstdp, and the port register port.cr1 . rstdp and port.cr1 . pd bits, are set after the global reset. a valid initialization sequence would be to clear the port.cr1 . pd bit, write to all of the configuration registers to set them in the desired modes, then clear the gl.cr1 . rstdp and port.cr1 . rstdp bits. this would cause the logic in the port to start up in a repeatable sequence. the device can also be initialized by clearing the gl.cr1 . rstdp, port.cr1 . rstdp and port.cr1 . pd them writing to all of the configuration registers to set them in the desired modes, and clearing all of the latched status bits. the second initialization scheme could cause the device to temporarily go into modes of operation that were not requested, but will quickly go into the requested modes of operation. some o f the io pins are put in a known state at reset. the transmit liu outputs txp and txn are quiet and will not drive positive or negative pulses. the global io pins (gpio[7:0]) are set as inputs at global reset. the port output pins (tlclk, tpos/tdat, tneg, tohclk, tohsof, tsofo/tden, tclko/tgclk, roh, rohclk, rohsof, rser, rsofo/rden, rclko/rgclk) are driven low at global or port reset and should stay low until after the port power - down port.cr1 . pd and port data path reset port.cr1 . rstdp bits are cleared. the processor port three - state output pins (d[15:0], rdy , int ) are forced into the high impedance state when the rst pin is active, but not when the gl.cr1 . rst bit is active. after reset, the device will be in the default configuration:: the latched status bits are enabled to be cleared on write. the clad is disabled. the global 8kref and one - second timers are disabled. the line interface is in b3zs mode and the liu is disabled and the transmit line pins are also disabled. the frame mode is ds3 c - bit with automatic downstream ais on los or oof is enabled and automatic rdi on lof, los, sef or ais is enabled and automatic febe is enabled. tr ansmit clock comes from the refclk pin. the pin inversion on all pins is disabled. individual blocks are reset and powered down when not used determined by the settings in the line mode bits port.cr2 . lm[2:0] and fr amer mode bits port.cr2 . fm[2:0].
ds3170 ds3/e3 single - chip transceiver 66 of 230 10.4 global resources 10.4.1 clock rate adapter (clad) the clock rate adapter is composed of a pll block to create the internal clock which can be used for the transmit clock and/or liu referenc e clock from a clock input on the reference input (refclk) pin. the device needs one of two (ds3 or e3) internal clock rates. the input reference clock frequency can be either 44.736, 34.368. 77.78, 51.84 or 19.44 mhz. the receive liu is supplied a referen ce clock from the clad. the receive liu selects the clock frequency based upon the mode the user selects via the fm bits. the clad output is also available as a transmit clock source if selected via the port.cr2 .c ladc register bit. the user must supply at least one of the five rates (44.736, 34.368. 77.78, 51.84 or 19.4 mhz) to the refclk pin. the clad[2:0] bits informs the pll of the frequency applied to the pins. selection of the clock applied to the liu and op tionally the transmitter is controlled by the fm bits (located in port.cr2 ). the clad allows maximum flexibility to the user. the user may supply any of the five clock rates and use the clad to convert the rate to the particular clock rate needed for his application. the clad pll is enabled when the clad input reference clock is different from the clock required for the framing mode. the clad pll is disabled and the clad output clock is connected directly to the cl ad input clock (refclk) when the framing mode requires the same clock as the clad input reference clock. table 10- 11 . clad clock source settings clad[2:0] refclk (input) 000 44.736 mhz 001 34.368 mhz 010 51 .84 mhz 011 19.44 mhz 100 77.76 mhz 101 undefined 11x undefined 10.4.2 8 khz reference generation the global 8kref signal is used to generate the one second reference signal by dividing it by 8000. this signal can be derived from almost any clock source on the chip as well as the general purpose io pin gpio4. the port 8kref signal can be sourced from the transmit or receive clocks. the minimum input frequency stability of the 8kref input pin is +/ - 500 ppm. the global 8kref signal can come from an external 8000 hz reference connected to the gpio4 general purpose io pin by setting the gl.cr2 . g8kis bit. the global 8kref signal can be output on the gpio2 general purpose io pin when the gl.cr 2 .g8kos bit is set. the global 8kref signal can be derived from the clad pll or pins or come from any of the port 8kref signals by clearing gl.cr2 . g8kis bit and selecting the source using the gl.cr2 . the port 8kref signal can be derived from the transmit clock input pin or from the receive liu or input clock pin. the g8krs[2:0] bits. port.cr3 . the 8kref 8.000 khz signal is a simple divisor of 44736 khz (ds3 divided by 5592) or 33368 khz (e3 divided by 4296). the correct divisor for the port 8kref source is selected by the mode the port is configured for. the clad clock chosen for the cloc k source selects the correct divisor for the global 8kref. the 8kref signal is only as accurate as the clock source chosen to generate it. p8krs[1:0] bits are used to select which s ource. table 10-12 lists the selectable sources for global 8 khz referen ce.
ds3170 ds3/e3 single - chip transceiver 67 of 230 table 10- 12 . global 8 khz reference source table g8kis gl.cr2 . g8krs[1:0] gl.cr2 . source 0 00 none, the 8khz divider is disabl ed. 0 01 derived from clad output clock 0 10 8kref source selected by p8krs[1:0] 0 11 undefined 1 xx gpio4 table 10-13 lists the selectable sources for port 8 khz reference sources. table 10- 13 . port 8 khz reference source table port.cr3 . source p8krs[1:0] 0x undefined 10 internal receive framer clock 11 internal transmit framer clock fi gure 10-6 shows the 8 khz reference logic tree. figure 10- 6 . 8kref logic clock divider clock divider tx clock rx clock frame mode p8krs gpio4 ds3 clk e3 clk from clad frame mode g8krs g8kis global 8kref port 8kref 10.4.3 one second reference generation the one second reference signal is used as an option to update the performance registers on a precis e one second interval. the generated internal signal should be about 50% duty cycle and it is derived from the global 8 khz reference signal by dividing it by 8000. the low to high edge on this signal will set the gl.srl . onesl latched one second detect bit which can generate an interrupt when the gl.srie . onesie interrupt enable bit is set. the low to high edge can also be used to generate performance monitor updates when gl.cr1 . gpm[1:0]=1x.
ds3170 ds3/e3 single - chip transceiver 68 of 230 10.4.4 general - purpose io pins there are eight general - purpose io pins that can be used for general io, global signals and framer alarm signals. each pin is independently configurable to be a general - purpose in put, general - purpose output, global signal or framer alarm. two of the gpio pins can be programmed to output one or two framer alarm statuses. one of the two pins assigned to framer alarms can be programmed as global input or output signals. when the port is powered down or reset and gl.giocr . gpiox[1:0] = 01, the gpio pin will be an output driving low. the 8krefi, tmei, and pmu signals that can be sourced by the gpio pin will be driven low into the core logic when the gpio pin is not selected for the source of the signal. table 10-14 lists the purpose and control thereof of the general - purpose io pins. table 10- 14 . gpi o global signals pin global signal control bit gpio2 8krefo output gl.cr2 .g8kos gpio4 8krefi input gl.cr2 .g8kis gpio6 tmei input gl.cr1 . meims gpio8 pmu input gl.cr1 .gpm[1:0] table 10-15 describes the selection of mode for the gpio pins. table 10- 15 . g pio pin global mode select bits gl.giocr .gpiosx gpio pin mode 00 input 01 framer alarm status selected by port gpio 10 output logic 0 11 output logic 1 x = a or b, valid when a gpio pin is not selected for a g lobal signal table 10-16 lists the various port alarm monitors that can be output on the gpio pins. the gpio(a/b)[3:0] bits are located in the port.cr4 register.
ds3170 ds3/e3 single - chip transceiver 69 of 230 table 10- 16 . gpio port alarm monitor select gpio(a/b)[3:0] port.cr4 line los ds3/e3 oof ds3/e3 lof ds3/e3 ais ds3/e3 rai ds3 idle 0000 x 0001 x 0010 x 0011 x 0100 x 0101 x 0110 0111 1000 1001 1010 1011 x x x 1100 1101 x x x 1110 x x 1111 x x x x x x 10.4.5 performance monitor counter update details the performance monitor cou nters are designed to count at least one second of events before saturating to the maximum count. there is a status bit associated with some of the performance monitor counters that is set when the its counter is greater than zero, and a latched status bit that gets set when the counter changes from zero to one. there is also a latched status bit that gets set on every event that causes the error counter to increment. there is a read register for each performance monitor counter. the count value of the cou nter gets loaded into this register and the counter is cleared when the update - clear operation is performed. if there is an event to be counted at the exact moment (clock cycle) that the counter is to be cleared then the counter will be set to a value of o ne so that that event will be counted. the performance monitor update signal affects the counter registers of the following blocks: the bert, the ds3/e3 framer, the line encoder/decoder. the update - clear operation is controlled by the performance monitor update signal (pmu). the update - clear operation will update the error counter registers with the value of the error counter and also reset each counter. the pmu signal can be created in hardware or software. the hardware sources can come from the one seco nd counter or one of the general - purpose io pins, which can be programmed to source this signal. the software sources can come from one of the port control register bits or one of the global control register bits. when using the software update method, the pmu control bit should be set to initiate the process and when the pms status bit gets set, the pmu control bit should be cleared making it ready for the next update. when using the hardware update method, the pms bit will be set shortly after the hardwar e signal goes high, and cleared shortly after the hardware signal goes low. the latched pms signal can be used to generate an interrupt for reading the count registers. if the port is not configured for global pmu signals, the pms signal from that port sho uld be blocked from affecting the global pms status.
ds3170 ds3/e3 single - chip transceiver 70 of 230 figure 10- 7 . performance monitor update logic gl.sr .gpms port.sr .pms port.cr1 .pmu port.cr1 .pmum 1 0 00 01 1x gl.cr1 .gpm gl.cr1 .gpmu gpio8(gpmu) pin one sec perf counter other port counters pmu pms gtz 10.4.6 transmit manual error insertion transmit errors can be inserted in some of the functional blocks. these err ors can be inserted using register bits in the functional blocks, using the global gl.cr1 . tmei bit, using the port port.cr1 . tmei bit, or by using the gpio6 pin configured for t mei mode. there is a transmit error insertion register in the functional blocks that allow error insertion. the meims bit controls whether the error is inserted using the bits in the error insertion register or using error insertion signals external to th at block. when bit meims=0, errors are inserted using other bits in the transmit error insertion register. when bit meims=1, errors are inserted using a signal generated in the port or global control registers or using the external gpio6 pin configured for tmei operation.
ds3170 ds3/e3 single - chip transceiver 71 of 230 figure 10- 8 . transmit error insert logic bert error insert bert.teicr .meims bert.teicr error insertion bit 0 1 0 1 port.cr .meims port.cr .tmei 0 1 gl.cr1 .meims gl.cr1 .tmei gpio6 pin (tmei) 0 1 t3.teir .meims t3.teir error insertion bit 0 1 t3 error insert 10.5 port resources 10.5.1 loopbacks there are several loop back paths available. the following table lists the loopback modes available for analog loopback (a lb), line loopback (llb), payload loopback (plb) and diagnostic loopback (dlb). the lbm bits are located in table 10- 17 . loopback mode selections port.cr4 . lbm[2:0] alb llb plb dlb 000 0 0 0 0 001 1 0 0 0 010 0 1 0 0 011 0 0 1 0 10x 0 0 0 1 110 0 1 0 1 111 0 0 0 1
ds3170 ds3/e3 single - chip transceiver 72 of 230 figure 10-9 highlights where each loopback mode is located and gives an overall view of the various loopback paths available. figure 10- 9 . loopback modes ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder 10.5.1.1 analog loopback (alb) analog loopback is enabled by setting port.cr4 . lbm[2:0] = 001. analog loopback mode will not be enabled when the port is configured for loop timed mode (set via the port.cr3 . loopt bit). the analog loopback is a loopback as close to the pins as possible. when both the tx and rx liu is enabled, it loop s back txp and txn to rxp and rxn, respectively. if the transmit signals on txp and txn are not terminated properly, this loopback path may have data errors or loss of signal. when the liu is not enabled, it loops back tlclk,tpos / tdat,tneg to rlclk, rpo s / rdat , rneg. figure 10- 10 . alb mux rxp rxn txp txn rx liu tx liu
ds3170 ds3/e3 single - chip transceiver 73 of 230 10.5.1.2 line loopback (llb) line loopback is enabled by setting port.cr4 . lbm[2:0] = x10. dlb and llb are enabled at the same time whe n lbm[2:0] = 110, and only llb is enabled when lbm[2:0] = 010. the clock from the receive liu or the rlclk pin will be output to the transmit liu or tclko pin. the pos and neg data from the receive liu or the rpos and rneg pin will be sampled with the rece ive clock to time it to the liu or pin interface. when llb is enabled, unframed all ones ais can optionally be automatically enabled on the receive data path. this ais signal will be output on the rser pin in framed modes. when dlb and llb is enabled, th e ais signal will not be transmitted. see figure 10-9 . 10.5.1.3 payload loopback (plb) payload loopback is enabled by setting port.cr4 . lbm[2:0] = 011. the payload loopback copies the payload data from the receive framer to the transmit framer which then re - frames the payload before transmission. payload loopback is operational in all framing modes. when plb is enabled, unframed all ones ais transmission can optionally be au tomatically enabled on the receive data path. this ais signal will be output on the rser. in all plb modes, the tsofi input pin is ignored. the external transmit output pins tden and tsofo/tden can optionally be disabled by forcing a zero when plb is enab led. see figure 10-9 . 10.5.1.4 diagnostic loopback (dlb) diagnostic loopback is enabled by setting port.cr4 . lbm[2:0] = 1xx. dlb and llb are enabled at the same time when lb m[2:0] = 110, only dlb is enabled when lbm[2:0] = 10x or 111. the diagnostic loopback sends the transmit data, before line encoding, back to the receive side. transmit ais can still be enabled using port.cr1 .lais[2 :0] even when dlb is enabled. see figure 10-9 . 10.5.2 loss of signal propagation the loss of signal (los) is detected in the line decoder logic. in unipolar (uni) line interface modes los is never detected. the los signal from the line decoder is sent to the ds3/e3 framer and the top level payload ais logic except when dlb is activated. when dlb is activated the los signal to the framer and ais logic is never active. the los status in the line decoder status regi ster is valid in all frame and loop back modes, though it is always off in the line interface is in the uni mode. 10.5.3 ais logic there is ais logic in both the framers and at the top level logic of the port. the framer ais is enabled by setting the tais bit in the appropriate framer transmit control register (t3, e3 - g.751, e3 - g.832, or clear channel). the top level ais is enabled by setting the port.cr1 .lais[2:0] bits (see table 10-18 ). the ais signal is an unframed all ones pattern or a ds3 framed 101010? pattern depending on the fm[2:0] mode bits. the ds3 framed alarm indication signal (ais) is a ds3 signal with valid f - bits, m - bits, and p - bits (p 1 and p 2 ). the x -bi ts (x 1 and x 2 ) are set to one, all c - bits (c xy ) are set to zero, and the payload bits are set to a 1010 pattern starting with a one immediately after each overhead bit. the ds3 framed ais pattern is only available in ds3 modes. the unframed all ones patte rn is available in all framing modes including the ds3 modes. the transmit line interface can send both unframed all ones ais and ds3 framed ais patterns from either the ais generator in the framer or the ais generator at the top level. the ais signal gen erated in the framer can be initiated and terminated without introducing any errors in the signal. when the unframed ais signal is initiated or terminated, there will be no bpv or cv errors introduced, but there will be framing errors if a framed mode is e nabled. when the ds3 framed ais signal is initiated or terminated, in addition to no bpv or cv errors, there should be no framing or p - bit (parity) or cp - bit errors introduced. the ais signal generated at the top level will not generate bpv errors but ma y generate p - bit and cp - bit errors when the signal is initiated and terminated. the framed ds3 ais signal will not cause the far end receiver to re - sync when the signal is initiated, but it may cause a re - sync when terminated if the ds3 frame position in t he framer is changed while the ds3 ais signal is being generated. a sequence of events can be executed which will enable the initiation and termination of ds3 ais or unframed all ones at the top level without any errors introduced.
ds3170 ds3/e3 single - chip transceiver 74 of 230 the sequence will only w ork when the automatic ais generation is not enabled. cv and p - bit errors can occur when ais is automatically generated and can not be avoided. this sequence to generate an error free ds# ais at the top level is to have the ds3 ais or unframed all ones s ignal initiate in the ds3 framer, and a few frames sent before initiating or terminating the ds3 ais or unframed all ones at the top level. after the top level ais signal is activated, the ais signal in the framer can be terminated, dlb activated and diagn ostic patterns generated. the ds3 ais signal generated at the top level will not change frame alignment after starting even if the ds3 frame position in the framer is changed. the transmit line ais generator at the top level can generate ais signals even when the framer is looped back using dlb, but not when the line is looped back using llb. the ais signal generated in the framer will be looped back to the receive side when dlb is activated. the receive framer can detect both unframed all ones ais and d s3 framed ais patterns. when in ds3 framing modes, both framed ds3 ais and unframed all ones can be detected. in e3 framing modes e3 ais, which is unframed all ones, is detected. the receive payload interface going to the rser pin or the bert logic can hav e an unframed all ones ais signal replacing the receive signal, this is called payload ais. the all ones ais signal is generated from either the ds3/e3 framer or the downstream top level unframed all ones ais generator. the unframed all ones ais signal ge nerated in the framer will be looped back to the transmit side when plb is activated. the unframed all ones ais signal generated at the top level will be sent to the rser pin and other receive logic, but not to the transmit side while plb is activated. th e top level ais generator is used when a downstream ais signal is desired while payload loop back is activated and is enabled by default after rest and must be cleared during configuration. note that the downstream ais circuit in the framer, when a ds3 mo de is selected, enforces the oof to be active for 2.5 msec before activating when automatic ais in the framer is enabled. the top level downstream ais will be generated with no delay when oof is detected when automatic ais at the top level is enabled. the re is no detection of any ais signal on the transmit payload signal from the tser pin or anywhere on the transmit data path. the transmit ais generator at the top level can also be activated with a software bit or automatically when dlb is activated. the receive ais generator in the framer can be activated with a software bit, and automatically when ais, los or oof are detected. the receive payload ais generator at the top level can be activated with a software bit or automatically when los, ds3/e3 oof, ll b, or plb is activated. figure 10-11 shows the ais signal flow through the device. figure 10- 11 . ais signal flow ua1 ais 0 1 0 1 ua1 ais ds3/ ua1 ais 0 1 0 1 0 1 ds3/ ua1 ais 0 1 optional b3zs/ hdb3 decoder optional b3zs/ hdb3 encoder plb 0 1 dlb llb ds3/ua1 ais detector framer tais dais tais dais transmit line receive line transmit payload receive payload tsofo line/tributary side system/ trunk side
ds3170 ds3/e3 single - chip transceiver 75 of 230 table 10-18 lists the lais decodes for various line ais enable modes. table 10- 18 . line ais enable modes lais[1:0] port.cr1 frame mode description ais code 00 ds3 automatic ais when dlb is enabled ( port.cr4 .lbm = 1xx) ds3ais 00 e3 automatic ais when dlb is enabled ua1 01 any send ua1 ua1 10 ds3 send ais ds3ais 10 e3 send ais ua1 11 any disable none table 10-19 lists the pais decodes for various payload ais enable modes. table 10- 19 . payload (downstream) ais enable modes pais[2:0] port.cr1 when ais is sent ais code 000 always ua1 001 when llb (no dlb) active ua1 010 when plb active ua1 011 when llb(no dlb) or plb active ua1 100 when los (no dlb) active ua1 101 when oof active ua1 110 when oof, los. llb (no dlb), or plb active ua1 111 never none 10.5.4 loop timing mode loop timing mode is enabled by setting the port.cr3 .loopt bit. this mode replaces the clock from the tclki pin with the internal receive clock from either the rlclk pin if the rx liu is disabled, or the recovered clock from t he rx liu if it is enabled. the loop timing mode can be activated in any framing or line interface mode. 10.5.5 hdlc overhead controller the data signal to the receive hdlc controller will be forced to a one while still being clocked when the framer (ds3, e3), to which the hdlc is connected, detects lof or ais. forcing the data signal to all ones will cause an hdlc packet abort if the data started to look like a packet instead of allowing a bad, and possibly very long, hdlc packet. 10.5.6 trail trace there is a single tr ail trace controller for use in line maintenance protocols. the e3 - g.832 framer has access to the trail trace controller. 10.5.7 bert there is a bit error rate test (bert) circuit for use in generating and detecting test signals in the payload bits. the bert ca n generate and detect prbs patterns up to 2^32 - 1 bits as well as repeating patterns up to 32 bits
ds3170 ds3/e3 single - chip transceiver 76 of 230 long. the generated bert signal replaces the data on the tser pin in framed modes when the bert is enabled by setting the port.cr1.bena. when the bert is enab led the tden and rden pins will still be active but the data on the tser pin will be discarded. 10.5.8 system port pins the system port pins have multiple functions based on the framing mode the device is in as well as other pin mode select bits. 10.5.8.1 transmit system port pins the transmit system pins are tsofi, tser, tsofo / tden, and tclko / tgclk. they have different functions based on the framing mode and other pin mode bits. unused input pin functions should drive a logic zero into the device circuits expecting a signal from that pin. the control bits that configure the pins? modes are port.cr2 . fm[2:0], port.cr3 . tpfpe, port.cr3 . tsofos and port.cr3 . tclks. table 10-20 to table 10-22 describe the function selected by the fm bits and other pin mode bits f or the multiplexed pins. table 10- 20 . tsofi input pin functions fm[2:0] port.cr2 pin function 0xx (frm) tsofi 1xx (ufrm) not used table 10- 21 . tsofo/tden/output pin functions fm[2:0] port.cr2 tsofos port.cr3 pin function 0xx (frm) 0 tden 0xx (frm) 1 tsofo 1xx (ufrm) x high table 10- 22 tclko/tgclk output pin functions fm[2:0] port.cr2 tclks port.cr3 pin function gap source 0xx (frm) 0 tgclk tden 0xx (f rm) 1 tclko none 1xx (ufrm) x tclko none 10.5.8.2 receive system port pins the receive system pins are rser, rsofo / rden and rclko / rgclk. they have different functions based on the framing mode and other pin mode bits. unused input pin functions should drive a logic zero into the device circuits expecting a signal from that pin. the control bits that configure these pins are port.cr2 . fm[2:0], port.cr3 . rpfpe, port.cr3 . rsofos and port.cr3 . rclks. table 10-23 to table 10-24 describe the function selecte d by the fm bits and other pin mode bits for the multiplexed pins.
ds3170 ds3/e3 single - chip transceiver 77 of 230 table 10- 23 . rsofo/rden output pin functions fm[2:0] port.cr2 rsofos port.cr3 pin function 0xx (frm) 0 rden 0xx (frm) 1 rsofo 1xx (ufrm) x high table 10- 24 . rclko/rgclk output pin functions fm[2:0] port.cr2 rclks port.cr3 pin function gap source 0xx (frm) 0 rgclk rden 0xx (frm) 1 rclko none 1xx (ufrm) x rclko none 10.5.9 framing modes the framing modes are selected independently of the line interface modes using the port.cr2 . fm[2:0] con trol bits. different blocks are used in different framing modes. the bit error test (bert) function can be enabled in any mode. the liu, ja and line encoder/decoder blocks are selected by the line mode (lm[2:0]) code. table 10- 25 . framing mode select bits fm[2:0] fm[2:0] description line code figure 0 00 ds3 c - bit framed b3zs/ami/uni 0 01 figure 7 - 1 ds3 m23 framed b3zs/ami/uni 0 10 figure 7 - 1 e3 g.751 famed hdb3/ami/uni 0 11 figure 7 - 1 e3 g.832 framed hdb3/ami/uni 1 00 figure 7 - 1 ds3 unframed b3zs/ami/ uni 1 01 figure 7 - 2 undefined --- 1 10 e3 unframed hdb3/ami/uni 1 11 figure 7 - 2 undefined --- 10.5.10 line interface modes the line interface modes can be selected semi - independently of the framing modes using the port.cr2 . lm[2:0] control bits. the major blocks controlled are the transmit liu (tx liu), receive liu (rx liu), jitter attenuator (ja) and the line encoder/decoder. the line encoder/decoder is used for b3zs, hdb3 and ami line interface encoding modes. the line encoder - decoder block is not used for line encoding or decoding in the uni mode but the bpv counter in it can be used to count external pulses on the rneg / rclv pin. the jitter attenuator ( ja) can be off (off) or put in either the transmit (tx) or receive (rx) path with the tx liu or rx liu. both tx liu and rx liu can be enabled (on) or disabled (off). the ?analog loop back? (alb) is available when the liu is enabled or disabled. it is an ac tual loop back of the analog positive and negative pulses from the tx liu to the rx liu when the liu is enabled. if the liu is disabled, it is a digital loop back of the tlclk, tpos, tneg signals to the rlclk, rpos and rneg signals. when the line is con figured for b3zs/hdb3/ami line codes, the line codes are determined by the framing mode and the ami line mode selection is controlled by the tzcds and rzcds bits in the line encoder/decoder blocks. the ds3 modes select the b3zs line coding, the e3 modes se lect the hdb3 line codes. refer to table 10-26 for configuration.
ds3170 ds3/e3 single - chip transceiver 78 of 230 table 10- 26 . line mode select bits lm[2:0] line.tcr . tzsd & line.rcr .rzsd lm[2:0] ( port.cr2 ) line code liu ja 0 000 b3zs/hdb3 off off 0 001 b3zs/hdb3 on off 0 010 b3zs/hdb3 on tx 0 011 b3zs/hdb3 on rx 1 000 ami o ff off 1 001 ami on off 1 010 ami on tx 1 011 ami on rx x 1xx uni off off
ds3170 ds3/e3 single - chip transceiver 79 of 230 10.6 ds3/e3 framer / formatter 10.6.1 general description the receive ds3/e3 framer receives a unipolar ds3/e3 signal, determines frame alignment and extracts the ds3/e3 overhead in the receive direction. the transmit ds3/e3 formatter receives a ds3/e3 payload, generates framing, inserts ds3/e3 overhead, and outputs a unipolar ds3/e3 signal in the transmit direction. the receive ds3/e3 framer receives a ds3/e3 signal from the receive liu or rdat (or rpos and rneg), determines the frame alignment, extracts the ds3/e3 overhead, and outputs the payload with frame and overhead the transmit ds3/e3 formatter receives a ds3/e3 payload on tser, generates a ds3/e3 frame, optionally inserts ds3/e3 overhead, and transmits the ds3/e3 signal. refer to figure 10-12 for the location of the ds3/e3 framer/formatter blocks in the ds3170. figure 10- 12 . framer detailed block diagram ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder 10.6.2 features 10.6.2.1 transmit formatter ? programmable ds3 or e3 formatter ? accepts a ds3 (m23 or c - bit) or e3 (g.751 or g.832) signal and performs ds3/e3 overhead generation. ? arbitrary framing format support ? generates a signal with an arbit rary framing format. the line overhead/stuff periods are added into the data stream using an overhead mask signal. ? generates alarms and errors ? ds3 alarm conditions (ais, rdi, and idle) and errors (framing, parity, and febe), or e3 alarm conditions (ais a nd rdi/rai) and errors (framing, parity, and rei) can be inserted into the outgoing data stream. ? externally controlled serial ds3/e3 overhead insertion port ? can insert all ds3 or e3 overhead via a serial interface. ds3/e3 overhead insertion is fully cont rolled via the serial overhead interface. ? hdlc overhead insertion ? an hdlc channel can be inserted into the ds3 or e3 data stream. ? feac insertion ? a feac channel can be inserted into the ds3 or e3 data stream. ? trail trace insertion ? inputs and inserts t he g.832 e3 tr byte. 10.6.2.2 receive framer ? programmable ds3 or e3 framer ? accepts a ds3 (m23 or c - bit) or e3 (g.751 or g.832) signal and performs ds3/e3 overhead termination.
ds3170 ds3/e3 single - chip transceiver 80 of 230 ? arbitrary framing format support ? accepts a signal with an arbitrary framing format. t he line overhead/stuff periods are removed from the data stream using an overhead mask signal. ? detects alarms and errors ? detects ds3 alarm conditions (sef, oomf, oof, lof, cofa, ais, aic, rdi, and idle) and errors (framing, parity, and febe), or e3 alar m conditions (oof, lof, cofa, ais, and rdi/rai) and errors (framing, parity, and rei). ? serial ds3/e3 overhead extraction port ? extracts all ds3 or e3 overhead and outputs it on a serial interface. ? hdlc overhead extraction ? an hdlc channel can be extracte d from the ds3 or e3 data stream. ? feac extraction ? a feac channel can be extracted from the ds3 or e3 data stream. ? trail trace extraction ? extracts and outputs the g.832 e3 tr byte. 10.6.3 transmit formatter the transmit formatter receives a ds3 or e3 data str eam and performs framing generation, error insertion, overhead insertion, and ais/idle generation for c - bit ds3, m23 ds3, g.751 e3, or g.832 e3 framing protocols. the bits in a byte are transmitted msb first, lsb last. when they are input serially, they ar e input in the order they are to be transmitted. the bits in a byte in an outgoing signal are numbered in the order they are transmitted, 1 (msb) to 8 (lsb). however, when a byte is stored in a register, the msb is stored in the highest numbered bit (7), a nd the lsb is stored in the lowest numbered bit (0). this is to differentiate between a byte in a register and the corresponding byte in a signal. 10.6.4 receive framer the receive framer receives the incoming ds3,or e3, ine/tributary data stream, performs approp riate framing, and terminates and extracts the associated overhead bytes. the receive framer processes a c - bit format ds3, m23 format ds3, g.751 format e3, or g.832 format e3 data stream, performing framing, performance monitoring, overhead extraction, a nd generates downstream ais, if necessary . the bits in a byte are received msb first, lsb last. when they are output serially, they are output msb first, lsb last. the bits in a byte in an incoming signal are numbered in the order they are received, 1 (msb ) to 8 (lsb). however, when a byte is stored in a register, the msb is stored in the highest numbered bit (7), and the lsb is stored in the lowest numbered bit (0). this is to differentiate between a byte in a register and the corresponding byte in a signa l. some bits, bit groups, or bytes (data) are integrated before being stored in a register. integration requires the data to have the same new data value for five consecutive occurrences before the new data value will be stored in the data register. unless stated otherwise, integrated data may have an associated unstable indication. integrated data is considered unstable if the received data value does not match the currently stored (integrated) data value or the previously received data value for eight con secutive occurrences. the unstable condition is terminated when the same value is received for five consecutive occurrences. 10.6.4.1.1 receive ds3 framing ds3 framing determines the ds3 frame boundary. in order to identify the ds3 frame boundary, first the subframe boundary must be found. the subframe boundary is found by identifying the subframe alignment bits f x1 , f x2 , f x3 , and f x4 , which have a value of one, zero, zero, and one respectively. see figure 10-13 . o nce the subframe boundary is found, the multiframe frame boundary can be found. the multiframe boundary is found by identifying the multiframe alignment bits m 1 , m 2 , and m 3 , which have a value of zero, one, and zero respectively. the ds3 framer is an off - l ine framer that only updates the data path frame counters when either an out of frame (oof) or an out of multiframe (oomf) condition is present. the use of an off - line framer reduces the average time required to reframe, and reduces data loss caused by bur st error . the ds3 framer has a maximum average reframe time (mart) of approximately 1.0 ms.
ds3170 ds3/e3 single - chip transceiver 81 of 230 figure 10- 13 . ds3 frame format 680 bits 7 sub- frames x 1 x 2 p 1 p 2 m 1 m 2 m 3 f 11 f 21 f 31 f 41 f 51 f 61 f 71 f 12 f 22 f 32 f 42 f 52 f 62 f 72 f 13 f 23 f 33 f 43 f 53 f 63 f 73 f 14 f 24 f 34 f 44 f 54 f 64 f 74 c 11 c 21 c 31 c 41 c 51 c 61 c 71 c 12 c 22 c 32 c 42 c 52 c 62 c 72 c 13 c 23 c 33 c 43 c 53 c 63 c 73 the subframe framer continually searches four adjacent bit positions for a subframe boundary. a subframe alignment bit (f - bit) checker checks each bit position. all four bit positions must fail before any other bit positions are checked for a subframe boundary. there are 170 possible bit positions that must be checked, and four positions are checked simultaneously. therefore up to 43 checks may be needed to identify the subframe boundary. the subframe framer enables the multiframe frame once it has identified a subframe boundary. refer to figure 10-14 for the subframe framer state diagram. figure 10- 14 . ds3 subframe framer state diagram sync load verify all 4 bit positions failed 2 f-bits loaded 3 bit positions failed or 16 f-bits verified all 4 bit positions failed the multiframe framer checks for a multiframe boundary. when the multiframe framer identifies a multi frame boundary, it updates the data path frame counters if either an oof or oomf condition is present. the multiframe framer waits until a subframe boundary has been identified. then, each bit position is checked for the multiframe
ds3170 ds3/e3 single - chip transceiver 82 of 230 boundary. the multiframe boundary is found by identifying the three multiframe alignment bits (m - bits). since there are seven multiframe bits and three bits are required to identify the multiframe boundary, up to 9 checks may be needed to find the multiframe boundary. once the mu ltiframe boundary is identified, it is checked in each subsequent frame. t he data path frame counters are updated if the three multiframe alignment bits are error free, and an oof or oomf condition exists . if the multiframe framer checks more than fifteen multiframe bit (x - bits, p - bits, and m - bits) positions without identifying the multiframe boundary, the multiframe framer times out, and forces the subframe framer back into the load state. refer to figure 10-15 for the multiframe framer state diagram. 10.6.4.1.2 receive ds3 performance monitoring performance monitoring checks the ds3 frame for alarm conditions and errors. the alarm conditions detected are oomf, oof, sef, lof, cofa, los, ais, idle, rua1, and rdi. t he errors accumulated are framing, p - bit parity, c - bit parity (c- bit format only), and far - end block error (febe) (c - bit format only) errors. an out of multiframe (oomf) condition is declared when a multiframe alignment bit (m - bit) error has been detected in two or more of the last four consecutive ds3 frames, or when a manual resynchronization is requested. an oomf condition is terminated when no m - bit errors have been detected in the last four consecutive ds3 frames, or when the ds3 framer updates the da ta path frame counters. refer to figure 10-15 for the multiframe framer state diagram. figure 10- 15 . ds3 multiframe framer state diagram sync load verify timeout 2 multiframe loaded m-bits identified m-bit error and timeout m-bit error if multiframe al ignment oof is disabled, an out of frame (oof) condition is declared when three or more out of the last sixteen consecutive subframe alignment bits (f - bits) have been errored, or a manual resynchronization is requested. if multiframe alignment oof is enabl ed, an oof condition is declared when three or more out of the last sixteen consecutive f - bits have been errored, when an oomf condition is declared, or when a manual resynchronization is requested. if multiframe alignment oof is disabled, an oof condition is terminated when none of the last sixteen consecutive f - bits has been errored, or when the ds3 framer updates the data path frame counters. if multiframe alignment oof is enabled, an oof condition is terminated when an oomf condition is not active and n one of the last sixteen consecutive f - bits has been errored, or when the ds3 framer updates the data path frame counters. multiframe alignment oof is programmable (on or off). a severely errored frame (sef) condition is declared when three or more out of t he last sixteen consecutive f - bits have been errored, or when a manual resynchronization is requested. an sef condition is terminated when an oof condition is absent.
ds3170 ds3/e3 single - chip transceiver 83 of 230 a loss of frame (lof) condition is declared by the lof integration counter when it has be en active for a total of t ms. the lof integration counter is active (increments count) when an oof condition is present, it is inactive (holds count) when an oof condition is absent, and it is reset when an oof condition is absent for t continuous ms. t i s programmable (0, 1, 2, or 3). an lof condition is terminated when an oof condition is absent for t continuous ms. a change of frame alignment (cofa) is declared when the ds3 framer updates the data path frame counters with a frame alignment that is diffe rent from the current data path ds3 frame alignment. a loss of signal (los) condition is declared when the b3zs encoder is active, and it declares an los condition. an los condition is terminated when the b3zs encoder is inactive, or it terminates an los c ondition. an alarm indication signal (ais) is a ds3 signal with valid f - bits and m - bits. the x - bits (x 1 and x 2 ) are set to one, the p - bits (p 1 and p 2 ) are set to zero, all c - bits (c xy ) are set to zero, and the payload bits are set to a 1010 pattern startin g with a one immediately after each ds3 overhead bit. an ais signal is present when a ds3 frame is received with valid f - bits and m - bits, both x - bits set to one, both p - bits set to zero, all c- bits set to zero, and all but seven or fewer payload data bits matching the ds3 overhead aligned 1010 pattern. an ais signal is absent when a ds3 frame is received that does not meet the aforementioned criteria for an ais signal being present. the ais integration counter declares an ais condition when it has been act ive for a total of 10 to 17 ds3 frames. the ais integration counter is active (increments count) when an ais signal is present, it is inactive (holds count) when an ais signal is absent, and it is reset when an ais signal is absent for 10 to 17 consecutive ds3 frames. an ais condition is terminated when an ais signal is absent for 10 to 17 consecutive ds3 frames. a receive unframed all 1?s (rua1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less zeros are detected and an oof c ondition is continuously present . a rua1 condition is terminated if in each of 4 consecutive 2047 bit windows, six or more zeros are detected or an oof condition is continuously absent. an idle signal (idle) is a ds3 signal with valid f - bits, m - bits, and p- bits (p 1 and p 2 ). the x - bits (x 1 and x 2 ) are set to one, c 31 , c 32 , and c 33 are set to zero, and the payload bits are set to a 1100 pattern starting with 11 immediately after each overhead bit. in c - bit mode, an idle signal is present when a ds3 frame is received with valid f - bits, m - bits, and p - bits, both x - bits set to one, c 31 , c 32 , and c 33 set to zero, and all but seven or fewer payload data bits matching the t3 overhead aligned 1100 pattern. in m23 mode, an idle signal is present when a t3 frame is re ceived with valid f - bits, m - bits, and p - bits, both x - bits set to one, and all but seven or fewer payload data bits matching the overhead aligned 1100 pattern. an idle signal is absent when a ds3 frame is received that does not meet aforementioned criteria for an idle signal being present. the idle integration counter declares an idle condition when it has been active for a total of 10 to 17 ds3 frames. the idle integration counter is active (increments count) when an idle signal is present, it is inactive (holds count) when an idle signal is absent, and it is reset when an idle signal is absent for 10 to 17 consecutive ds3 frames. an idle condition is terminated when an idle signal is absent for 10 to 17 consecutive ds3 frames. a remote defect indication ( rdi) condition (also called a far - end sef/ais defect condition) is declared when four consecutive ds3 frames are received with the x - bits (x 1 and x 2 ) set to zero. an rdi condition is terminated when four consecutive ds3 frames are received with the x - bits set to one. a ds3 framing format mismatch (ds3fm) condition is declared when the ds3 format programmed (m13, c - bit) does not match the incoming ds3 signal framing format. a ds3fm condition is terminated when the incoming ds3 signal framing format is the same format as programmed. framing errors are determined by comparing f - bits and m - bits to their expected values. the type of framing errors accumulated is programmable (oofs, f & m, f, or m). an oof error increments the count whenever an oof condition is first detected . an f & m error increments the count once for each f - bit or m - bit that does not match its expected value (up to 31 per ds3 frame). an f error increments the count once for each f - bit that does not match its expected value (up to 28 per ds3 frame). an m error increments the count once for each m - bit that does not match its expected value (up to 3 per ds3 frame). p- bit parity errors are determined by calculating the parity of the current ds3 frame (payload bits only), and comparing the calcul ated parity to the p - bits (p 1 and p 2 ) in the next ds3 frame. if the calculated parity does not match p 1 or p 2 , a single p - bit parity error is declared. c - bit parity errors (c- bit format only) are determined by calculating the parity of the current ds3 fram e (payload bits only), and comparing the calculated parity to the c - bits in subframe three (c 31 , c 32 , and c 33 ) in the next ds3 frame. if the calculated parity does not match c 31 , c 32 , or c 33 , a single c - bit parity error is declared.
ds3170 ds3/e3 single - chip transceiver 84 of 230 febe errors (c - bit for mat only) are determined by the c - bits in subframe four (c 41 , c 42 , and c 43 ). a value of 111 indicates no error and any other value indicates an error. the receive alarm indication (rai) bit will be set high in the transmitter when one or more of the indica ted alarm conditions is present, and low when all of the indicated alarm conditions are absent. setting the receive alarm indication on los, sef, lof, or ais is individually programmable (on or off). the application identification channel (aic) is stored i n a register bit. it is determined from the c 11 bit. the aic is set to one (c - bit format) if the c 11 bit is set to one in thirty - one consecutive multiframes. the aic is set to zero (m23 format) if the c 11 bit is set to zero in four of the last thirty -one c onsecutive multiframes. note: the stored aic bit must not change when an los, oof, or ais condition is present. a febe is transmitted by default upon reception of a ds3 frame in which a c - bit parity error or a framing error is detected and counted. 10.6.5 c - bit ds3 framer/formatter 10.6.5.1 transmit c - bit ds3 frame processor the c - bit ds3 frame format is shown in figure 10-13 . figure 10- 13 . ds3 frame format 680 bits 7 sub- frames x 1 x 2 p 1 p 2 m 1 m 2 m 3 f 11 f 21 f 31 f 41 f 51 f 61 f 71 f 12 f 22 f 32 f 42 f 52 f 62 f 72 f 13 f 23 f 33 f 43 f 53 f 63 f 73 f 14 f 24 f 34 f 44 f 54 f 64 f 74 c 11 c 21 c 31 c 41 c 51 c 61 c 71 c 12 c 22 c 32 c 42 c 52 c 62 c 72 c 13 c 23 c 33 c 43 c 53 c 63 c 73 table 10-27 shows the function of each overhead bit in the ds3 frame
ds3170 ds3/e3 single - chip transceiver 85 of 230 table 10- 27 . c - bit ds3 frame overhead bit definitions bit definition x 1 , x 2 remote de fect indication (rdi) p 1 , p 2 parity bits m 1 , m 2 , and m 3 multiframe alignment bits f xy subframe alignment bits c 11 application identification channel (aic) c 12 reserved c 13 far - end alarm and control (feac) signal c 21 , c 22 , and c 23 unused c 31 , c 32 , and c 33 c - bit parity bits c 41 , c 42 , and c 43 far - end block error (febe) bits c 51 , c 52 , and c 53 path maintenance data link (or hdlc) bits c 61 , c 62 , and c 63 unused c 71 , c 72 , and c 73 unused x 1 and x 2 are the remote defect indication (rdi) bits (a lso referred to as the far - end sef/ais bits). p 1 and p 2 are the parity bits used for line error monitoring. m 1 , m 2 , and m 3 are the multiframe alignment bits. f xy are the subframe alignment bits. c 11 is the application identification channel (aic). c 12 is r eserved for future network use, and has a value of one. c 13 is the far - end alarm and control (feac) signal. c 21 , c 22 , and c 23 are unused, and have a value of one. c 31 , c 32 , and c 33 are the c - bit parity bits used for path error monitoring. c 41 , c 42 , and c 43 are the far - end block error (febe) bits used for remote path error monitoring. c 51 , c 52 , and c 53 are the path maintenance data link (or hdlc) bits. c 61 , c 62 , and c 63 are unused, and have a value of one. c 71 , c 72 , and c 73 are unused, and have a value of on e. the x - bit, p - bit, m - bit, c- bit, and f - bit positions are overhead bits, and the other bit positions in the t3 frame are payload bits regardless of how they are marked by tden. 10.6.5.2 transmit c - bit ds3 frame generation c - bit ds3 frame generation receives the in coming payload data stream, and overwrites all of the overhead bit locations. the multiframe alignment bits (m 1 , m 2 , and m 3 ) are overwritten with the values zero, one, and zero (010) respectively. the subframe alignment bits (f x1 , f x2 , f x3 , and f x4 ) are ov erwritten with the values one, zero, zero, and one (1001) respectively. the x - bits (x 1 and x 2 ) are both overwritten with the remote defect indicator (rdi). the rdi source is programmable (automatic, 1, or 0). if the rdi is generated automatically, the x -bi ts are set to zero when one or more of the indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are absent. automatically setting rdi on los, sef, lof, or ais is individually programmable (on or off). the p - bits (p 1 and p 2 ) are both overwritten with the calculated payload parity from the previous ds3 frame. the payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has been completed. p - bit generation is programmable (on or off). the p - bits will be generated if either p - bit generation is enabled or frame generation is enabled. the bits c 11 , c 12 , c 21 , c 22 , c 23 , c 61 , c 62 , c 63 , c 71 , c 72 , and c 73 are all overwritten with a one. the bit c 13 is overwritten with the far - end alarm and control (feac) data input from the transmit feac controller.
ds3170 ds3/e3 single - chip transceiver 86 of 230 the bits c 31 , c 32 , and c 33 are all overwritten with the calculated payload parity from the previous ds3 frame. the bits c 41 , c 42 , and c 43 are all overwritten with the far -en d block error (febe) bit. the febe bit can be generated automatically or inserted from a register bit. the febe bit source is programmable (automatic or register). if the febe bit is generated automatically, it is zero when at least one c - bit parity error has been detected during the previous frame. the bits c 51 , c 52 , and c 53 are overwritten with the path maintenance data link input from the hdlc controller. once all of the ds3 overhead bits have been overwritten, the data stream is passed on to error inser tion. if frame generation is disabled, the incoming ds3 signal is passed on to error insertion. frame generation is programmable (on or off). note: p - bit generation may still be performed even if frame generation is disabled. 10.6.5.3 transmit c - bit ds3 error inse rtion error insertion inserts various types of errors into the different ds3 overhead bits. the types of errors that can be inserted are framing errors, p - bit parity errors, c- bit parity errors, and far - end block error (febe) errors. the framing error inse rtion mode is programmable (f - bit, m - bit, sef, or oomf). an f- bit error is a single subframe alignment bit (f xy ) error. an m - bit error is a single multiframe alignment bit (m 1 , m 2 , or m 3 ) error. an sef error is an error in all the subframe alignment bits i n a subframe (f x1 , f x2 , f x3 , and f x4 ). an oomf error is a single multiframe alignment bit (m 1 , m 2 , or m 3 ) error in two consecutive ds3 frames. a p- bit parity error is generated by is inverting the value of the p - bits ( p 1 and p 2 ) in a single ds3 frame. p -bi t parity error(s) can be inserted one error at a time, or continuously. the p - bit parity error insertion mode (single or continuous) is programmable. a c - bit parity error is generated by is inverting the value of the c 31 , c 32 , and c 33 bits in a single ds3 frame. c - bit parity error(s) can be inserted one error at a time, or continuously. the c - bit parity error insertion mode (single or continuous) is programmable. a febe error is generated by forcing the c 41 , c 42 , and c 43 bits in a single multiframe to zero. febe error(s) can be inserted one error at a time, or continuously. the febe error insertion rate (single or continuous) is programmable . each error type (framing, p - bit parity, c- bit parity, or febe) has a separate enable. continuous error insertion mod e inserts errors at every opportunity. single error insertion mode inserts an error at the next opportunity when requested. the framing multi - error modes (sef or oomf) insert the indicated number of error(s) at the next opportunities when requested; i.e. , a single request will cause multiple errors to be inserted. the requests can be initiated by a register bit(tsei) or by the manual error insertion input (tmei). the error insertion initiation type (register or input) is programmable. the insertion of ea ch particular error type is individually enabled. once all error insertion has been performed, the data stream is passed on to overhead insertion . 10.6.5.4 transmit c - bit ds3 overhead insertion overhead insertion can insert any (or all) of the ds3 overhead bits int o the ds3 frame. the ds3 overhead bits x 1 , x 2 , p 1 , p 2 , m x , f xy , and c xy can be sourced from the transmit overhead interface (tohclk, toh, tohen, and tohsof). the p - bits (p 1 and p 2 ) and c 31 , c 32 , and c 33 bits are received as an error mask (modulo 2 addition of the input bit and the internally generated bit). the ds3 overhead insertion is fully controlled by the transmit overhead interface. if the transmit overhead data enable signal (tohen) is driven high, then the bit on the transmit overhead signal (toh) i s inserted into the output data stream. insertion of bits using the toh signal overwrites internal overhead insertion. 10.6.5.5 transmit c - bit ds3 ais/idle generation c - bit ds3 ais/idle generation overwrites the data stream with ais or an idle signal. if transmit idle is enabled, the data stream payload is forced to a 1100 pattern with two ones immediately following each ds3 overhead bit. m 1 , m 2 , and m 3 bits are overwritten with the values zero, one, and zero (010) respectively. f x1 , f x2 , f x3 , and f x4 bits are ove rwritten with the values one, zero, zero, and one (1001) respectively. x 1 and x 2 are overwritten with 11. and, p 1 , p 2, c 31 , c 32 , and c 33 are overwritten with the calculated payload parity from the previous output ds3 frame. if transmit ais is enabled, the data stream payload is forced to a 1010 pattern with a one immediately following each ds3 overhead bit. m 1 , m 2 , and m 3 bits are overwritten with the values zero, one, and zero (010) respectively. f x1 , f x2 , f x3 , and f x4 bits are overwritten with the values one, zero, zero, and one (1001) respectively. x 1 and x 2 are overwritten with 11. p 1 , p 2, c 31 , c 32 , and c 33 are overwritten with the calculated payload parity from the previous output ds3 frame. and, c x1 , c x2 , and c x3 (x 3) are overwritten with 000. ais w ill overwrite a transmit idle signal.
ds3170 ds3/e3 single - chip transceiver 87 of 230 10.6.5.5.1 receive c - bit ds3 frame format the ds3 frame format is shown in figure 10-13 . x 1 and x 2 are the remote defect indication (rdi) bits (also referred to as the far -end sef/ais bits). p 1 and p 2 are the parity bits used for line error monitoring. m 1 , m 2 , and m 3 are the multiframe alignment bits that define the multiframe boundary. f xy are the subframe alignment bits that define the subframe boundary. note: both the m - bits and f - bits define the ds3 frame boundary. c 11 is the application identification channel (aic). c 12 is reserved for future network use, and has a value of one. c 13 is the far - end alarm and control (feac) signal. c 21 , c 22 , and c 23 are unused, and have a val ue of one. c 31 , c 32 , and c 33 are the c - bit parity bits used for path error monitoring. c 41 , c 42 , and c 43 are the far - end block error (febe) bits used for remote path error monitoring. c 51 , c 52 , and c 53 are the path maintenance data link (or hdlc) bits. c 61 , c 62 , and c 63 are unused, and have a value of one. c 71 , c 72 , and c 73 are unused, and have a value of one. 10.6.5.5.2 receive c - bit ds3 overhead extraction overhead extraction extracts all of the ds3 overhead bits from the c - bit ds3 frame. all of the ds3 overhead bit s x 1 , x 2 , p 1 , p 2 , m x , f xy , and c xy are output on the receive overhead interface (roh, rohsof, and rohclk). the p 1 , p 2 , c 31 , c 32 , and c 33 bits are output as an error indication (modulo 2 addition of the calculated parity and the bit). the c 13 bit is sent ov er to the receive feac controller. the c 51 , c 52 , and c 53 bits are sent to the receive hdlc overhead controller. 10.6.6 m23 ds3 framer/formatter 10.6.6.1 transmit m23 ds3 frame processor the m23 ds3 frame format is shown in figure 1 0 -13 . table 10-28 defines the framing bits for m23 ds3. x 1 and x 2 are the remote defect indication (rdi) bits (also referred to as the far - end sef/ais bits). p 1 and p 2 are the parity bits us ed for line error monitoring. m 1 , m 2 , and m 3 are the multiframe alignment bits. f xy are the subframe alignment bits. c 11 is the application identification channel (aic). c x1 , c x2 , and c x3 are the stuff control bits for tributary #x. the x - bit, p - bit, m -bit , c - bit, and f - bit positions are overhead bits, and the remainder of the bit positions in the t3 frame are payload bits regardless of how they are marked by tden. table 10- 28 . m23 ds3 frame overhead bit defini tions bit definition x 1 , x 2 remote defect indication (rdi) p 1 , p 2 parity bits m 1 , m 2 , and m 3 multiframe alignment bits f xy subframe alignment bits c 11 application identification channel (aic) c x1 , c x2 , and c x3 stuff control bits for tributary #x 10.6.6.2 transmit m23 ds3 frame generation m23 ds3 frame generation receives the incoming payload data stream, and overwrites all of the ds3 overhead bit locations. the multiframe alignment bits (m 1 , m 2 , and m 3 ) are overwritten with the values zero, one, and ze ro (010) respectively. the subframe alignment bits (f x1 , f x2 , f x3 , and f x4 ) are overwritten with the values one, zero, zero, and one (1001) respectively. the x - bits (x 1 and x 2 ) are both overwritten with the remote defect indicator (rdi). the rdi source is programmable (automatic, 1, or 0). if the rdi is generated automatically, the x - bits are set to zero when one or
ds3170 ds3/e3 single - chip transceiver 88 of 230 more of the indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are absent. automatically setting rdi on los, sef, lof, or ais is individually programmable (on or off). the p - bits (p 1 and p 2 ) are both overwritten with the calculated payload parity from the previous ds3 frame. the payload parity is calculated by performing modulo 2 addition of all of th e payload bits after all frame processing has been completed. p - bit generation is programmable (on or off). the p - bits will be generated if either p - bit generation is enabled or frame generation is enabled. if c - bit generation is enabled, the bit c 11 is ov erwritten with an alternating one zero pattern, and all of the other c - bits (c xy ) are overwritten with zeros. if c - bit generation is disabled, then all of the c- bit timeslots (c xy ) will be treated as payload data, and passed through. c - bit generation is pr ogrammable (on or off). note: overhead insertion may still overwrite the c - bit time slots even if c- bit generation is disabled. once all of the ds3 overhead bits have been overwritten, the data stream is passed on to error insertion. if frame generation is disabled, the incoming ds3 signal is passed on directly to error insertion. frame generation is programmable (on or off). note: p - bit generation may still be performed even if frame generation is disabled. 10.6.6.3 transmit m23 ds3 error insertion error inserti on inserts various types of errors into the different ds3 overhead bits. the types of errors that can be inserted are framing errors and p - bit parity errors. the framing error insertion mode is programmable (f - bit, m - bit, sef, or oomf). an f- bit error is a single subframe alignment bit (f xy ) error. an m - bit error is a single multiframe alignment bit (m 1 , m 2 , or m 3 ) error. an sef error is an error in all the subframe alignment bits in a subframe (f x1 , f x2 , f x3 , and f x4 ). an oomf error is a single multiframe alignment bit (m 1 , m 2 , or m 3 ) error in each of two consecutive ds3 frames. a p- bit parity error is generated by is inverting the value of the p - bits ( p 1 and p 2 ) in a single ds3 frame. p - bit parity error(s) can be inserted one error at a time, or continuous ly. the p - bit parity error insertion mode (single or continuous) is programmable . each error type (framing or p - bit parity) has a separate enable. continuous error insertion mode inserts errors at every opportunity. single error insertion mode inserts an error at the next opportunity when requested. the framing multi - error insertion modes (sef or oomf) insert the indicated number of error(s) at the next opportunities when requested; i.e., a single request will cause multiple errors to be inserts. the re quests can be initiated by a register bit(tsei) or by the manual error insertion input (tmei). the error insertion request source (register or input) is programmable . the insertion of each particular error type is individually enabled. once all error inser tion has been performed, the data stream is passed on to overhead insertion . 10.6.6.4 transmit m23 ds3 overhead insertion overhead insertion can insert any (or all) of the ds3 overhead bits into the ds3 frame. the ds3 overhead bits x 1 , x 2 , p 1 , p 2 , m x , f xy , and c xy can be sourced from the transmit overhead interface (tohclk, toh, tohen, and tohsof). the p - bits (p 1 and p 2 ) are received as an error mask (modulo 2 addition of the input bit and the internally generated bit). the ds3 overhead insertion is fully controlle d by the transmit overhead interface. if the transmit overhead data enable signal (tohen) is driven high, then the bit on the transmit overhead signal (toh) is inserted into the output data stream. insertion of bits using the toh signal overwrites interna l overhead insertion. 10.6.6.5 transmit m23 ds3 ais/idle generation m23 ds3 ais/idle generation overwrites the data stream with ais or an idle signal. if transmit idle is enabled, the data stream payload is forced to a 1100 pattern with two ones immediately follow ing each ds3 overhead bit. m 1 , m 2 , and m 3 bits are overwritten with the values zero, one, and zero (010) respectively. f x1 , f x2 , f x3 , and f x4 bits are overwritten with the values one, zero, zero, and one (1001) respectively. x 1 and x 2 are overwritten with 11. p 1 and p 2 are overwritten with the calculated payload parity from the previous output ds3 frame. and, c 31 , c 32 , and c 33 are overwritten with 000. if transmit ais is enabled, the data stream payload is forced to a 1010 pattern with a one immediately fol lowing each ds3 overhead bit. m 1 , m 2 , and m 3 bits are overwritten with the values zero, one, and zero (010) respectively. f x1 , f x2 , f x3 , and f x4 bits are overwritten with the values one, zero, zero, and one (1001) respectively. x 1 and x 2 are overwritten wi th 11. p 1 and p 2 are overwritten with the calculated payload parity from the previous ds3 frame. and, c x1 , c x2 , and c x3 are overwritten with 000. ais will overwrite a transmit idle signal.
ds3170 ds3/e3 single - chip transceiver 89 of 230 10.6.6.5.1 receive m23 ds3 frame format the ds3 frame format is shown in figure 10-13 . the x 1 and x 2 are the remote defect indication (rdi) bits (also referred to as the far - end sef/ais bits). p 1 and p 2 are the parity bits used for line error monitoring. m 1 , m 2 , and m 3 are the mul tiframe alignment bits that define the multiframe boundary. f xy are the subframe alignment bits that define the subframe boundary. note: both the m - bits and f - bits define the ds3 frame boundary. c 11 is the application identification channel (aic). c x1 , c x 2 , and c x3 are the stuff control bits for tributary #x. 10.6.6.5.2 receive m23 ds3 overhead extraction overhead extraction extracts all of the ds3 overhead bits from the m23 ds3 frame. all of the ds3 overhead bits x 1 , x 2 , p 1 , p 2 , m x , f xy , and c xy are output on the re ceive overhead interface (roh, rohsof, and rohclk). the p 1 and p 2 bits are output as an error indication (modulo 2 addition of the calculated parity and the bit). 10.6.6.5.3 receive ds3 downstream ais generation downstream ds3 ais (all ?1?s) can be automatically gen erated on an oof, los, or ais condition or manually inserted. if automatic downstream ais is enabled, downstream ais is inserted when an los or ais condition is declared, or no earlier than 2.25 ms and no later than 2.75 ms after an oof condition is declar ed. automatic downstream ais is programmable (on or off). if manual downstream ais insertion is enabled, downstream ais is inserted. manual downstream ais insertion is programmable (on or off). downstream ais is removed when all oof, los, and ais conditio ns are terminated and manual downstream ais insertion is disabled. 10.6.7 g.751 e3 framer/formatter 10.6.7.1 transmit g.751 e3 frame processor the g.751 e3 frame format is shown in figure 10-16 . fas is the frame alignme nt signal. a is the alarm indication bit used to indicate the presence of an alarm to the remote terminal equipment. n is the national use bit reserved for national use. figure 10- 16 . g.751 e3 frame format fas 1524 bit payload 384 bits 4 rows a n 10.6.7.2 transmit g.751 e3 frame generation g.751 e3 frame generation receives the incoming payload data stream, and overwrites all of the e3 overhead bit locations. the first ten bits of the frame are overwritten with the frame alignment signal (fas) which has a value of 1111010000b. the eleventh bit of the frame is overwritten with the alarm indication (a) bit. the a bit can be generated automatically, sourced from the transmit feac controller, set to one, or set to zero. the a bit source is programmable (automa tic, feac, 1, or 0). if the a bit is generated automatically, it is set to one when one or more of the indicated alarm conditions is present, and set to zero when all of the indicated alarm conditions are absent. automatically setting rdi on los, lof, or a is is individually programmable (on or off). the twelfth bit of the frame is overwritten with the national use (n) bit. the n bit can be sourced from the transmit feac controller, sourced from the transmit hdlc overhead controller, set to one, or set to ze ro. the n bit source is programmable (feac, hdlc, 1, or 0). note: the feac controller will source one bit per frame regardless of whether the a bit only, the n bit only, or both are programmed to be sourced from the feac controller.
ds3170 ds3/e3 single - chip transceiver 90 of 230 once all of the e3 ov erhead bits have been overwritten, the data stream is passed on to error insertion. if frame generation is disabled, the incoming e3 signal is passed on directly to error insertion. frame generation is programmable (on or off). 10.6.7.3 transmit g.751 e3 error ins ertion error insertion inserts framing errors into the frame alignment signal (fas). the type of error(s) inserted into the fas is programmable (errored fas bit or errored fas). an errored fas bit is a single bit error in the fas. an errored fas is an erro r in all ten bits of the fas (a value of 0000101111b is inserted in the fas). framing error(s) can be inserted one error at a time, or in four consecutive frames. the framing error insertion number (single or four) is programmable . single error insertion m ode inserts an error at the next opportunity when requested. the multi - error insertion mode inserts the indicated number of errors at the next opportunities when requested. i.e., a single request will cause multiple errors to be inserted. the requests can be initiated by a register bit(tsei) or by the manual error insertion input (tmei). the error insertion initiation type (register or input) is programmable . the insertion of each particular error type is individually enabled. once all error insertion has b een performed, the data stream is passed on to overhead insertion . 10.6.7.4 transmit g.751 e3 overhead insertion overhead insertion can insert any (or all) of the e3 overhead bits into the e3 frame. the fas, a bit, and n bit can be sourced from the transmit overhe ad interface (tohclk, toh, tohen, and tohsof). the e3 overhead insertion is fully controlled by the transmit overhead interface. if the transmit overhead data enable signal (tohen) is driven high, then the bit on the transmit overhead signal (toh) is inser ted into the output data stream. insertion of bits using the toh signal overwrites internal overhead insertion. 10.6.7.5 transmit g.751 e3 ais generation g.751 e3 ais generation overwrites the data stream with ais. if transmit ais is enabled, the data stream (pay load and e3 overhead) is forced to all ones. 10.6.7.6 receive g.751 e3 frame processor the g.751 e3 frame format is shown in figure 10-16 . fas is the frame alignment signal. a is the alarm indication bit used to i ndicate the presence of an alarm to the remote terminal equipment. n is the national use bit reserved for national use. 10.6.7.6.1 receive g.751 e3 framing g.751 e3 framing determines the g.751 e3 frame boundary. the frame boundary is found by identifying the frame alignment signal (fas), which has a value of 1111010000b. the framer is an off - line framer that updates the data path frame counters when an out of frame (oof) condition has been detected. the use of an off - line framer reduces the average time required to reframe, and reduces data loss caused by burst error . the g.751 e3 framer checks each bit position for the fas. the frame boundary is set once the fas is identified. since, the fas check is performed one bit at a time, up to 1536 checks may be needed to fi nd the frame boundary. th e data path frame counters are updated if an error free fas is received for two additional frames, and an oof condition is present, or if a manual frame resynchronization has been initiated . 10.6.7.6.2 receive g.751 e3 performance monitoring performance monitoring checks the e3 frame for alarm conditions. the alarm conditions detected are oof, lof, cofa, los, ais, rua1, and rai. an out of frame (oof) condition is declared when four consecutive frame alignment signals (fas) contain one or more errors or at the next fas check when a manual reframe is requested. an oof condition is terminated when three consecutive fas?s are error free or the g.751 e3 framer updates the data path frame counters. a loss of frame (lof) condition is declared by the lof integration counter when it has been active for a total of t ms. the lof integration counter is active (increments count) when an oof condition is present, it is inactive (holds count) when an oof condition is absent, and it is reset when an oof condit ion is absent for t continuous ms. t is programmable (0, 1, 2, or 3). an lof condition is terminated when an oof condition is absent for t continuous ms.
ds3170 ds3/e3 single - chip transceiver 91 of 230 a change of frame alignment (cofa) is declared when the g.751 e3 framer updates the data path frame co unters with a frame alignment that is different from the current data path frame alignment. a loss of signal (los) condition is declared when the hdb3 encoder is active, and it declares an los condition. an los condition is terminated when the hdb3 encoder is inactive, or it terminates an los condition. an alarm indication signal (ais) condition is declared when 4 or less zeros are detected in each of two consecutive frame periods. an ais condition is terminated when 5 or more zeros are detected in each of two consecutive frame periods. a receive unframed all 1?s (rua1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less zeros are detected and an oof condition is continuously present. a rua1 condition is terminated if in each of 4 consecutive 2047 bit windows, six or more zeros are detected or an oof condition is continuously absent. a remote alarm indication (rai) condition is declared when four consecutive frames are received with the a bit (first bit after the fas) set to one. an rai condition is terminated when four consecutive frames are received with the a bit set to zero. only framing errors are accumulated. framing errors are determined by comparing the fas to its expected value. the type of framing errors accumulated is pr ogrammable (oofs, bit, or word). an oof error increments the count whenever an oof condition is first detected. a bit error increments the count once for each bit in the fas that does not match its expected value (up to 10 per frame. a word error increment s the count once for each fas that does not match its expected value (up to 1 per frame). the receive alarm indication (rai) signal is high when one or more of the indicated alarm conditions is present, and low when all of the indicated alarm conditions ar e absent. setting the receive alarm indication on los, oof, lof, or ais is individually programmable (on or off). 10.6.7.6.3 receive g.751 e3 overhead extraction overhead extraction extracts all of the e3 overhead bits from the g.751 e3 frame. the fas, a bit, and n bit are output on the receive overhead interface (roh, rohsof, and rohclk). in addition, the a bit is integrated and stored in a register along with a change indication, and can be output over the receive feac controller. the n bit is integrated and stored in a register along with a change indication, is sent to the receive hdlc overhead controller, and can also be sent to the receive feac controller. the bit sent to the receive feac controller is programmable (a or n). 10.6.7.6.4 receive g.751 downstream ais generat ion downstream g.751 e3 ais can be automatically generated on an oof, los, or ais condition or manually inserted. if automatic downstream ais is enabled, downstream ais is inserted when an los, oof, or ais condition is declared. automatic downstream ais is programmable (on or off). if manual downstream ais insertion is enabled, downstream ais is inserted. manual downstream ais insertion is programmable (on or off). downstream ais is removed when all oof, los, and ais conditions are terminated and manual dow nstream ais insertion is disabled. rpdt will be forced to all ones during downstream ais. 10.6.8 g.832 e3 framer/formatter 10.6.8.1 transmit g.832 e3 frame processor the g.832 e3 frame format is shown in figure 10-17 .
ds3170 ds3/e3 single - chip transceiver 92 of 230 figure 10- 17 . g.832 e3 frame format fa1 em tr ma nr gc fa2 530 byte payload 59 columns 9 rows figure 10- 18 . ma byte format rdi - remote defect indicator rei - remote error indicator sl - signal label mi - multi-frame indicator tm - timing marker rdi rei sl sl sl mi mi tm msb 1 lsb 8 table 10-29 shows the function of each overhead bit in the ds3 frame. table 10- 29 . g.832 e3 frame overhead bit definitions byte definition fa1, fa2 frame alignment bytes em error monitoring byte tr trail trace byte ma maintenance and adapt ion byte nr network operator byte gc general purpose communication channel byte
ds3170 ds3/e3 single - chip transceiver 93 of 230 fa1 and fa2 are the frame alignment bytes. em is the error monitoring byte used for path error monitoring. tr is the trail trace byte used for end - to - end connectivity verif ication. ma is the maintenance and adaptation byte used for far - end path status and performance monitoring. nr is the network operator byte allocated for network operator maintenance purposes. gc is the general purpose communications channel byte allocated for user communications purposes. 10.6.8.2 transmit g.832 e3 frame generation g.832 e3 frame generation receives the incoming payload data stream, and overwrites all of the e3 overhead byte locations. the first two bytes of the first row in the frame are overwrit ten with the frame alignment bytes fa1 and fa2, which have a value of f6h and 28h respectively. the first byte in the second row of the frame is overwritten with the em byte which is a bip - 8 calculated over all of the bytes of the previous frame after all frame processing (frame generation, error insertion, overhead insertion, and ais generation) has been performed. the first byte in the third row of the frame is overwritten with the tr byte which is input from the transmit trail trace controller. the firs t byte in the fourth row of the frame is overwritten with the ma byte (see figure 10-18 ), which consists of the rdi bit, rei bit, payload type, multiframe indicator, and timing source indicator. the rdi bit can be generated automatically, set to one, or set to zero. the rdi source is programmable (automatic, 1, or 0). if the rdi is generated automatically, it is set to one when one or more of the indicated alarm conditions is present, and set to zero when all of the indicated alarm conditions are absent. automatically setting rdi on los, lof, or ais is individually programmable (on or off). the rei bit can be generated automatically or inserted from a register bit. the rei source is programmable (automatic or register). if rei is generated automatically, it is one when at least one parity error has been detected during the previous frame. the payload type is sourced from a register. the three register bits are inserted in the third, fourth, and fifth bits o f the ma byte in each frame. the multiframe indicator and timing marker bits can be directly inserted from a 3 - bit register or generated from a 4- bit register. the multiframe indicator and timing marker insertion type is programmable (direct or generated). when the multiframe indicator and timing marker bits are directly inserted, the three register bits are inserted in the last three bits of the ma byte in each frame. when the multiframe indicator and timing marker bits are generated, the four timing sourc e indicator bits are transferred in a four - frame multiframe, msb first. the multiframe indicator bits (sixth and seventh bits of the ma byte) identify the phase of the multiframe (00, 01, 10, or 11), and the timing marker bit (eighth bit of the ma byte) co ntains the corresponding timing source indicator bit (tmabr register bits tti3, tti2, tti1, or tti0 respectively). note: the initial phase of the multiframe is arbitrarily chosen. the first byte in the fifth row of the frame is overwritten with the nr by te which can be sourced from a register, from the transmit feac controller, or from the transmit hdlc controller. the nr byte source is programmable (register, feac, or hdlc). note: the hdlc controller will source eight bits per frame period regardless o f whether the nr byte only, gc byte only, or both are programmed to be sourced from the hdlc controller. the first byte in the sixth row of the frame is overwritten with the gc byte which can be sourced from a register or from the transmit hdlc controller. the gc byte source is programmable (register or hdlc). once all of the e3 overhead bytes have been overwritten, the data stream is passed on to error insertion. if frame generation is disabled, the incoming e3 signal is passed on directly to error inserti on. frame generation is programmable (on or off). 10.6.8.3 transmit g.832 e3 error insertion error insertion inserts various types of errors into the different e3 overhead bytes. the types of errors that can be inserted are framing errors, bip - 8 parity errors, and remote error indication (rei) errors. the type of framing error(s) inserted is programmable (errored frame alignment bit or errored frame alignment word). a frame alignment bit error is a single bit error in the frame alignment word (fa1 or fa2). a frame alignment word error is an error in all sixteen bits of the frame alignment word (the values 09h and d7h are inserted in the fa1 and fa2 bytes respectively). framing error(s) can be inserted one error at a time, or four consecutive frames. the framing erro r insertion mode (single or four) is programmable.
ds3170 ds3/e3 single - chip transceiver 94 of 230 the type of bip - 8 error(s) inserted is programmable (errored bip - 8 bit, or errored bip - 8 byte). an errored bip - 8 bit is inverting a single bit error in the em byte. an errored bip - 8 byte is inverting all e ight bits in the em byte. bip -8 error(s) can be inserted one error at a time, or continuously. the bip - 8 error insertion mode (single or continuous) is programmable. an rei error is generated by forcing the second bit of the ma byte to a one. rei error(s) can be inserted one error at a time, or continuously. the rei error insertion mode (single or continuous) is programmable . each error type (framing, bip - 8, or rei) has a separate enable. continuous error insertion mode inserts errors at every opportunity. single error insertion mode inserts an error at the next opportunity when requested. the framing multi - error insertion mode inserts the indicated number of errors at the next opportunities when requested. i.e., a single request will cause multiple errors to be inserted. the requests can be initiated by a register bit(tsei) or by the manual error insertion input (tmei). the error insertion request source (register or input) is programmable . the insertion of each particular error type is individually enabled . once all error insertion has been performed, the data stream is passed on to overhead insertion . 10.6.8.4 transmit g.832 e3 overhead insertion overhead insertion can insert any (or all) of the e3 overhead bytes into the e3 frame. the e3 overhead bytes fa1, fa2, e m, tr, ma, nr, and gc can be sourced from the transmit overhead interface (tohclk, toh, tohen, and tohsof). the em byte is sourced as an error mask (modulo 2 addition of the input em byte and the generated em byte). the e3 overhead insertion is fully contr olled by the transmit overhead interface. if the transmit overhead data enable signal (tohen) is driven high, then the bit on the transmit overhead signal (toh) is inserted into the output data stream. insertion of bits using the toh signal overwrites int ernal overhead insertion. 10.6.8.5 transmit g.832 e3 ais generation g.832 e3 ais generation overwrites the data stream with ais. if transmit ais is enabled, the data stream (payload and e3 overhead) is forced to all ones. 10.6.8.6 receive g.832 e3 frame processor the g.832 e3 frame format is shown in figure 10-17 . fa1 and fa2 are the frame alignment bytes. em is the error monitoring byte used for path error monitoring. tr is the trail trace byte used for end -to - end conne ctivity verification. ma is the maintenance and adaptation byte used for far - end path status and performance monitoring (see figure 10-18 ). nr is the network operator byte allocated for network operator maintenance purposes. gc is the general purpose communications channel byte allocated for user communications purposes. 10.6.8.7 receive g.832 e3 framing g.832 e3 framing determines the g.832 e3 frame boundary. the frame boundary is found by identifying the frame alignment bytes fa1 and fa2, which have a value of f6h and 28h respectively. the framer is an off - line framer that updates the data path frame counters when an out of frame (oof) condition has been detected. the use of an off - line framer reduces the averag e time required to reframe, and reduces data loss caused by burst error . the g.832 e3 framer checks each bit position for the frame alignment word (fa1 and fa2). the frame boundary is set once the frame alignment word is identified. since, the frame alignm ent word check is performed one bit at a time, up to 4296 checks may be needed to find the frame boundary. th e data path frame counters are updated if an error free frame alignment word is received for two additional frames, and an oof condition is present . 10.6.8.8 receive g.832 e3 performance monitoring performance monitoring checks the e3 frame for alarm conditions and errors. the alarm conditions detected are oof, lof, cofa, los, ais, rua1, and rdi. the errors accumulated are framing, parity, and remote error in dication (rei) errors. an out of frame (oof) condition is declared when four consecutive frame alignment words (fa1 and fa2) contain one or more errors, when 986 or more frames out of 1,000 frames has a bip - 8 block error, or at the next framing word check when a manual reframe is requested. an oof condition is terminated when three consecutive frame alignment words (fa1 and fa2) are error free or the g.832 e3 framer updates the data path frame counters. a loss of frame (lof) condition is declared by the lo f integration counter when it has been active for a total of t ms. the lof integration counter is active (increments count) when an oof condition is present, it is inactive (holds count) when an oof condition is absent, and it is reset when an oof conditio n is absent for t continuous ms. t is programmable (0, 1, 2, or 3). an lof condition is terminated when an oof condition is absent for t continuous ms.
ds3170 ds3/e3 single - chip transceiver 95 of 230 a change of frame alignment (cofa) is declared when the g.832 e3 framer updates the data path frame coun ters with a frame alignment that is different from the current data path frame alignment. a loss of signal (los) condition is declared when the hdb3 encoder is active, and it declares an los condition. an los condition is terminated when the hdb3 encoder i s inactive, or it terminates an los condition. an alarm indication signal (ais) condition is declared when 7 or less zeros are detected in each of two consecutive frame periods that do not contain a frame alignment word. an ais condition is terminated when 8 or more zeros are detected in each of two consecutive frame periods. a receive unframed all 1?s (rua1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less zeros are detected and an oof condition is continuously present. a ru a1 condition is terminated if in each of 4 consecutive 2047 bit windows, six or more zeros are detected or an oof condition is continuously absent. a remote defect indication (rdi) condition is declared when four consecutive frames are received with the rd i bit (first bit of ma byte) set to one. an rdi condition is terminated when four consecutive frames are received with the rdi bit set to zero. three types of errors are accumulated, framing, parity, and remote error indication (rei) errors. framing errors are determined by comparing fa1 and fa2 to their expected values. the type of framing errors accumulated is programmable (oofs, bit, byte, or word). an oof error increments the count whenever an oof condition is first detected. a bit error increments the count once for each bit in fa1 and each bit in fa2 that does not match its expected value (up to 16 per frame). a byte error increments the count once for each fa byte (fa1 or fa2) that does not match its expected value (up to 2 per frame). a word error in crements the count once for each fa word (both fa1 and fa2) that does not match its expected value (up to 1 per frame). parity errors are determined by calculating the bip - 8 (8 - bit interleaved parity) of the current e3 frame (overhead and payload bytes), a nd comparing the calculated bip - 8 to the em byte in the next frame. the type of parity errors accumulated is programmable (bit or block). a bit error increments the count once for each bit in the em byte that does not match the corresponding bit in the cal culated bip - 8 (up to 8 per frame). a block error increments the count if any bit in the em byte does not match the corresponding bit in the calculated bip - 8 (up to 1 per frame). rei errors are determined by the rei bit (second bit of ma byte). a one indica tes an error and a zero indicates no errors. the receive alarm indication (rai) signal is high when one or more of the indicated alarm conditions is present, and low when all of the indicated alarm conditions are absent. setting the receive alarm indicatio n on los, oof, lof, or ais is individually programmable (on or off). the receive error indication (rei) signal will transition from low to high once for each frame in which a parity error is detected. 10.6.8.9 receive g.832 e3 overhead extraction overhead extracti on extracts all of the e3 overhead bytes from the g.832 e3 frame. all of the e3 overhead bytes fa1, fa2, em, tr, ma, nr, and gc are output on the receive overhead interface (roh, rohsof, and rohclk). the em byte is output as an error indication (modulo 2 addition of the calculated bip - 8 and the em byte. the tr byte is sent to the receive trail trace controller. the payload type (third, fourth, and fifth bits of the ma byte) is integrated and stored in a register with change and unstable indications. the i ntegrated received payload type is also compared against an expected payload type. if the received and expected payload types do not match (see table 10-30 ), a mismatch indication is set.
ds3170 ds3/e3 single - chip transceiver 96 of 230 table 10- 30 . payload label match status expected received status 000 000 match 000 001 mismatch 000 xxx mismatch 001 000 mismatch 001 001 match 001 xxx match xxx 000 mismatch xxx 001 match xxx xxx match xxx yyy mism atch xxx and yyy equal any value other than 000 or 001; xxx yyy. the multiframe indicator and timing marker bits (sixth, seventh, and eighth bits of the ma byte) can be integrated and stored in three register bits or extracted, integrated, and stored in four register bits. the bits (three or four) are stored with a change indication. the multiframe indicator and timing marker storage type is programmable (integrated or extracted). when the multiframe indicator and timing marker bits are integrated, the l ast three bits of the ma byte are integrated and stored in three register bits. when the multiframe indicator and timing marker bits are extracted, four timing source indicator bits are transferred in a four - frame multiframe, msb first. the multiframe indi cator bits (sixth and seventh bits of the ma byte) identify the phase of the multiframe (00, 01, 10, or 11). the timing marker bit (eighth bit of the ma byte) contains the timing source indicator bit indicated by the multiframe indicator bits (first, secon d, third, or fourth bit respectively). the four timing source indicator bits are extracted from the multiframe, integrated, and stored in four register bits with unstable and change indications. the nr byte is integrated and stored in a register along with a change indication, it is sent to the receive feac controller, and it can be sent to the receive hdlc controller. the byte sent to the receive hdlc controller is programmable (nr or gc). the gc byte is integrated and stored in a register along with a cha nge indication, and can be sent to the receive hdlc controller. the byte sent to the receive hdlc controller is programmable (nr or gc). 10.6.8.10 receive g.832 downstream ais generation downstream g.832 e3 ais can be automatically generated on an oof, los, or ais condition or manually inserted. if automatic downstream ais is enabled, downstream ais is inserted when an los, oof, or ais condition is declared. automatic downstream ais is programmable (on or off). if manual downstream ais insertion is enabled, downstre am ais is inserted. manual downstream ais insertion is programmable (on or off). downstream ais is removed when all oof, los, and ais conditions are terminated and manual downstream ais insertion is disabled. rpdt will be forced to all ones during downstre am ais . 10.7 hdlc overhead controller 10.7.1 general description the ds3170 device contains a built - in hdlc controller with 256 byte fifos for insertion/extraction of ds3 pmdl, g.751 sn bit and g.832 nr/gc bytes. the hdlc overhead controller demaps hdlc overhead pack ets from the ds3/e3 data stream in the receive direction and maps hdlc packets into the ds3/e3 data stream in the transmit direction. the receive direction performs packet processing and stores the packet data in the fifo. it removes packet data from the fifo and outputs the packet data to the microprocessor via the register interface. the transmit direction inputs the packet data from the microprocessor via the register interface and stores the packet data in the fifo. it removes the packet data from the fifo and performs packet processing.
ds3170 ds3/e3 single - chip transceiver 97 of 230 the bits in a byte are received msb first, lsb last. when they are output serially, they are output msb first, lsb last. the bits in a byte in an incoming signal are numbered in the order they are received, 1 (msb) to 8 (lsb). however, when a byte is stored in a register, the msb is stored in the lowest numbered bit (0), and the lsb is stored in the highest numbered bit (7). this is to differentiate between a byte in a register and the corresponding byte in a signal. se e figure 10-19 for the location of hdlc controllers within the ds3170 device. figure 10- 19 . hdlc controller block diagram 10.7.2 features ? programmable inter - fra me fill ? the inter - frame fill between packets can be all 1?s or flags. ? programmable fcs generation / monitoring ? an fcs - 16 can be generated and appended to the end of the packet, and the fcs can be checked and removed from the end of the packet. ? programmab le bit reordering ? the packet data can be can be output msb first or lsb first from the fifo. ? programmable data inversion ? the packet data can be inverted immediately after packet processing on the transmit, and immediately before packet processing on th e receive. ? fully independent transmit and receive paths ? fully independent line side and register interface timing ? the data storage can be read from or written to via the microprocessor interface while all line side clocks and signals are inactive, and re ad from or written to via the line side while all microprocessor interface clocks and signals are inactive. 10.7.3 transmit fifo the transmit fifo block contains memory for 256 bytes of data with data status information and controller circuitry for reading and wr iting the memory. the transmit fifo controller functions include filling the memory, tracking the memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow conditions . the transmit fifo receives data and status from the microprocessor interface , and stores the data along with the data status information in memory . the transmit packet processor reads the data and data status information from the transmit fifo. the transmit fifo also outputs fifo fill statu s (empty/data storage available/full) via the microprocessor interface. all operations are byte based. the transmit fifo is considered empty when its memory does not contain any data. the transmit fifo is considered to have data storage available when its memory has a programmable number of bytes or more available for storage. the transmit fifo is considered full when it does not have any space available for storage. the transmit fifo accepts data from the register interface until full. if the transmit fif o is written to while the fifo is full, the write is ignored, and a fifo overflow condition is declared. the transmit packet processor reads the transmit fifo. if the transmit packet processor attempts to read the transmit fifo while it is empty, a fifo un derflow condition is declared. ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder
ds3170 ds3/e3 single - chip transceiver 98 of 230 10.7.4 transmit hdlc overhead processor the transmit hdlc overhead processor accepts data from the transmit fifo, performs bit reordering, fcs processing, stuffing, packet abort sequence insertion, and inter - frame padding. a byte i s read from the transmit fifo with a packet end status. when a byte is marked with a packet end indication, the output data stream will be padded with ffh and marked with a fifo empty indication if the transmit fifo contains less than two bytes or transmit packet start is disabled. transmit packet start is programmable (on or off). when the transmit packet processor reads the transmit fifo while it is empty, the output data stream is marked with an abort indication. once the transmit fifo is empty, the outp ut data stream will be padded with interframe fill until the transmit fifo contains two or more bytes of data and transmit packet start is enabled. bit reordering changes the bit order of each byte. if bit reordering is disabled, the outgoing 8 - bit data st ream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is input from the transmit fifo with the msb in tfd[0] and the lsb in tfd[7] of the transmit fifo data tfd[7:0]. if bit reordering is enabled, the outgoing 8 - bit data stream dt[1:8] is input fro m the transmit fifo with the msb in tfd[7] and the lsb in tfd[0] of the transmit fifo data tfd[7:0]. dt[1] is the first bit transmitted on the outgoing data stream. fcs processing calculates an fcs and appends it to the packet. fcs calculation is a crc -16 calculation over the entire packet. the polynomial used for the crc - 16 is x 16 + x 12 + x 5 + 1. the crc - 16 is inverted after calculation, and appended to the packet. for diagnostic purposes, an fcs error can be inserted. this is accomplished by appending the calculated crc - 16 without inverting it. fcs error insertion is programmable (on or off). when fcs processing is disabled, the packet is output without appending an fcs. fcs processing is programmable (on or off). stuffing inserts control data into the pac ket to prevent packet data from mimicking flags. stuffing is halted during fifo empty periods. the 8 - bit parallel data stream is multiplexed into a serial data stream, and bit stuffing is performed. bit stuffing consists of inserting a '0' directly followi ng any five contiguous '1's. stuffing is performed from a packet start until a packet end. inter - frame padding inserts inter - frame fill between the packet start and end flags when the fifo is empty. the inter - frame fill can be flags or '1's. if the inter - f rame fill is flags, flags (minimum two) are inserted until a packet start is received. if the inter - frame fill is all '1's, an end flag is inserted, ?1?s are inserted until a packet start is received, and a start flag is inserted after the ?1?s. the number of '1's between the end flag and start flag may not be an integer number of bytes, however, the inter - frame fill will be at least 15 consecutive '1's. if the fifo is not empty between a packet end and a packet start, then two flags are inserted between th e packet end and packet start. the inter - frame padding type is programmable (flags or ?1?s). packet abort insertion inserts a packet abort sequences as necessary. if a packet abort indication is detected, a packet abort sequence is inserted and inter - frame padding is done until a packet start is detected. the abort sequence is ffh. once all packet processing has been completed, the datastream is inserted into the ds3/e3 datastream at the proper locations. if transmit data inversion is enabled, the outgoing data is inverted after packet processing is performed. transmit data inversion is programmable (on or off). 10.7.5 receive hdlc overhead processor the receive hdlc overhead packet processor accepts data from the ds3/e3 framer and performs packet delineation, inte r- frame fill filtering, packet abort detection, destuffing, fcs processing, and bit reordering. if receive data inversion is enabled, the incoming data is inverted before packet processing is performed. receive data inversion is programmable (on or off). p acket delineation determines the packet boundary by identifying a packet start flag. each time slot is checked for a flag sequence (7eh). once a flag is found, if it is identified as a start or end flag, and the packet boundary is set. there may be a singl e flag (both end and start) between packets, there may be an end flag and a start flag with a shared zero (011111101111110) between packets, there may be an end flag and a start flag (two flags) between packets, or there may be an end flag, inter - frame fil l, and a start flag between packets. the flag check is performed one bit at a time. inter - frame fill filtering removes the inter - frame fill between a start flag and an end flag. all inter - frame fill is discarded. the inter - frame fill can be flags (0111111 0) or all '1's. when inter - frame fill is all ?1?s, the number of '1's between the end flag and the start flag may not be an integer number of bytes. when inter - frame fill is flags, the
ds3170 ds3/e3 single - chip transceiver 99 of 230 number of bits between the end flag and the start flag will be an integ er number of bytes (flags). any time there is less than 16 bits between two flags, the data will be discarded. packet abort detection searches for a packet abort sequence. between a packet start flag and a packet end flag, if an abort sequence is detected, the packet is marked with an abort indication, and all subsequent data is discarded until a packet start flag is detected. the abort sequence is seven consecutive ones. packet abort detection searches for a packet abort sequence. between a packet start fl ag and a packet end flag, if an abort sequence is detected, the packet is marked with an abort indication, and all subsequent data is discarded until a packet start flag is detected. the abort sequence is seven consecutive ones. destuffing removes the extr a data inserted to prevent data from mimicking a flag or an abort sequence. after a start flag is detected, destuffing is performed until an end flag is detected. destuffing consists of discarding any '0' that directly follows five contiguous '1's. after d estuffing is completed, the serial bit stream is demultiplexed into an 8 - bit parallel data stream and passed on with packet start, packet end, and packet abort indications. if there is less than eight bits in the last byte, an invalid packet status is set, and the packet is tagged with an abort indication. if a packet ends with five contiguous '1's, the packet will be processed as a normal packet regardless of whether or not the five contiguous '1's are followed by a '0'. fcs processing checks the fcs, disc ards the fcs bytes, and marks fcs erred packets . the fcs is checked for errors, and the last two bytes are removed from the end of the packet. if an fcs error is detected, the packet is marked with an fcs error indication. the hdlc controller performs fcs - 16 checking . fcs processing is programmable (on or off). if fcs processing is disabled, fcs checking is not performed, and all of the packet data is passed on. bit reordering changes the bit order of each byte. if bit reordering is disabled, the incoming 8 - bit data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is output to the receive fifo with the msb in rfd[0] and the lsb in rfd[7] of the receive fifo data rfd[7:0]. if bit reordering is enabled, the incoming 8 - bit data stream dt[1:8] is output to the receive fifo with the msb in rfd[7] and the lsb in rfd[0] of the receive fifo data rfd[7:0]. dt[1] is the first bit received from the incoming data stream. once all of the packet processing has been completed, the 8 - bit parallel data stream i s passed on to the receive fifo with packet start, packet end, and packet error indications. 10.7.6 receive fifo the receive fifo block contains memory for 256 bytes of data with data status information and controller circuitry for reading and writing the memory. the receive fifo controller controls filling the memory, tracking the memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow conditions. the receive fifo accepts data and data status from the receiv e packet processor and stores the data along with data status information in memory. the data is read from the receive fifo via the microprocessor interface. the receive fifo also outputs fifo fill status (empty/data available/full) via the microprocessor interface. all operations are byte based. the receive fifo is considered empty when it does not contain any data. the receive fifo is considered to have data available when there is a programmable number of bytes or more stored in the memory. the receive f ifo is considered full when it does not have any space available for storage. the receive fifo accepts data from the receive packet processor until full. if a packet start is received while full, the data is discarded and a fifo overflow condition is decla red. if any other packet data is received while full, the current packet being transferred is marked with an abort indication, and a fifo overflow condition is declared. once a fifo overflow condition is declared, the receive fifo will discard incoming dat a until a packet start is received while the receive fifo has sixteen or more bytes available for storage. if the receive fifo is read while the fifo is empty, the read is ignored, and an invalid data indication given. 10.8 trail trace controller 10.8.1 general descri ption the ds3170 has a dedicated trail trace buffer for e3 - g.832 link management the trail trace controller performs extraction and storage of the incoming g.832 trail access point identifier in a 16- byte receive register.
ds3170 ds3/e3 single - chip transceiver 100 of 230 the trail trace controller extrac ts/inserts e3 - g.832 trail access point identifiers using a 16- byte register(one for transmit, one for receive). the trail trace controller demaps a 16 - byte trail trace identifier from the e3- g.832 datastream in the receive direction and maps a trace iden tifier into the e3 - g.832 datastream in the transmit direction. the receive direction inputs the trace id data stream, performs trace id processing, and stores the trace identifier data in the data storage using line timing. it removes trace identifier dat a from the data storage and outputs the trace identifier data to the microprocessor via the microprocessor interface using register timing. the data is forced to all ones during los, lof and ais detection to eliminate false messages the transmit direction inputs the trace identifier data from the microprocessor via the microprocessor interface and stores the trace identifier data in the data storage using register timing. it removes the trace identifier data from the data storage, performs trace id process ing, and outputs the trace id data stream. refer to figure 10-20 for the location of the trail trace controller with the ds3170 device. figure 10- 20 . trai l trace controller block diagram 10.8.2 features ? programmable trail trace id ? the trail trace id controller can be programmed to handle a 16 - byte trail trace identifier (trail trace mode). ? programmable transmit trace id ? all sixteen bytes of the transmit tra il trace identifier are programmable. ? programmable receive expected trace id ? a 16 - byte expected trail trace identifier can be programmed. both a mismatch and unstable indication are provided. ? programmable trace id multiframe alignment ? the transmit side can be programmed to perform trail trace multiframe alignment insertion. the receive side can be programmed to perform trail trace multiframe synchronization. ? programmable bit reordering ? the trace identifier data can be output msb first or lsb first fr om the data storage. ? programmable data inversion ? the trace identifier data can be inverted immediately after trace id processing on the transmit side, and immediately before trail id processing on the receive side. ? fully independent transmit and receive sides ? fully independent line side and register interface timing ? the data storage can be read from or written to via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to via the line side while all microprocessor interface clocks and signals are inactive. 10.8.3 functional description the bits in a byte are received most significant bit (msb) first and least significant bit (lsb) last. when they are output serially, they are output msb first and lsb last. t he bits in a byte in an incoming signal are numbered in the ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder
ds3170 ds3/e3 single - chip transceiver 101 of 230 order they are received, 1 (msb) to 8 (lsb). however, when a byte is stored in a register, the msb is stored in the highest numbered bit (7), and the lsb is stored in the lowest numbered bit (0). this is to differentiate between a byte in a register and the corresponding byte in a signal. 10.8.4 transmit data storage the transmit data storage block contains memory for 16 bytes of data and controller circuitry for reading and writing the memory. the trans mit data storage controller functions include filling the memory and maintaining the memory read and write pointers . the transmit data storage receives data from the microprocessor interface , and stores the data in memory . the transmit trace id processor r eads the data from the transmit data storage. the transmit data storage contains the transmit trail trace identifier. note: the contents of the transmit trail (path) trace identifier memory will be random data immediately after power - up, and will not chang e during a reset ( rst or drst low). 10.8.5 transmit trace id processor the transmit trace id processor accepts data from transmit data storage, processes the data according to the transmit trace id mode, and outputs the serial trace id data stream. 10.8.6 transmit trail trace processing the transmit trail trace processing accepts data from the transmit data storage performs bit reordering and multiframe alignment insertion. bit reordering changes the bit order of each byte. if bit reordering is disabled, the outgoing 8 -b it data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is input from the transmit data storage with the msb in ttd[7] and the lsb in ttd[0] of the transmit trace id data ttd[7:0]. if bit reordering is enabled, the outgoing 8 - bit data strea m dt[1:8] is input from the transmit data storage with the msb is in ttd[0] and the lsb is in ttd[7] of the transmit trace id data ttd[7:0]. dt[1] is the first bit transmitted on the outgoing data stream. multiframe alignment insertion overwrites the msb o f each trail trace byte with the multiframe alignment signal. the msb of the first byte in the trail trace identifier is overwritten with a one, the msb of the other fifteen bytes in the trail trace identifier are overwritten with a zero. multiframe alignm ent insertion is programmable (on or off). if transmit data inversion is enabled, the outgoing data is inverted after trail trace processing is performed. transmit data inversion is programmable (on or off). if transmit trail trace identifier idle (idle) i s enabled, the trail trace data is overwritten with all zeros. transmit idle is programmable (on or off). 10.8.7 receive trace id processor the receive trace id processor receives the incoming serial trace id data stream and processes the incoming data according to the receive trace id mode, and passes the trace id data on to receive data storage. the bits in a byte are received msb first, lsb last. the bits in a byte in an incoming signal are numbered in the order they are received, 1 (msb) to 8 (lsb). however, w hen a byte is stored in a register, the msb is stored in the highest numbered bit (7), and the lsb is stored in the lowest numbered bit (0). this is to differentiate between a byte in a register and the corresponding byte in a signal. 10.8.8 receive trail trace p rocessing the receive trail trace processing accepts an incoming data line and performs trail trace alignment, trail trace extraction, expected trail trace comparison, and bit reordering. if receive data inversion is enabled, the incoming data is inverted before trail trace processing is performed. receive data inversion is programmable (on or off). trail trace alignment determines the trail trace identifier boundary by identifying the multiframe alignment signal. the multiframe alignment signal (mas) is lo cated in the msb of each byte ( figure 10-21 ). the mas bits are each checked for the multiframe alignment start bit, which is a one. once a multiframe alignment start bit is found, the remaining fifteen b its of the mas are verified as being zero. the mas check is performed one byte at a time. multiframe alignment is programmable (on or off). when multiframe alignment is disabled, the incoming bytes are sequentially stored starting with a random byte.
ds3170 ds3/e3 single - chip transceiver 102 of 230 figur e 10- 21 . trail trace byte (dt = trail trace data) bit 1 msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 lsb mas or dt [1] dt [2] dt [3] dt [4] dt [5] dt [6] dt [7] dt [8] trail trace extraction extracts the trail t race identifier from the incoming trail trace data stream, generates a trail trace identifier change indication, detects a trail trace identifier idle (idle) condition, and detects a trail trace identifier unstable (tiu) condition. the trail trace identifi er bytes are stored sequentially with the first byte (mas equals 1 if trail trace alignment is enabled) being stored in the first byte of memory. if the exact same nonzero trail trace identifier is received five consecutive times and it is different from t he receive trail trace identifier, a receive trail trace identifier update is performed, and the receive trail trace identifier change indication is set. an idle condition is declared when an all zeros trail trace identifier is received five consecutive t imes. an idle condition is terminated when a nonzero trail trace identifier is received five consecutive times or a tiu condition is declared. a tiu condition is declared if eight consecutive trail trace identifiers are received that do not match either th e receive trail trace identifier or the previously stored current trail trace identifier. the tiu condition is terminated when a nonzero trail trace identifier is received five consecutive times or an idle condition is declared. expected trail trace compar ison compares the received and expected trail trace identifiers. the comparison is a 7 - bit comparison of the seven least significant bits (dt[2:8] (see figure 10-21 ) of each trail trace identifier byte ( the multiframe alignment signal is ignored). if the received and expected trail trace identifiers do not match, a trail trace identifier mismatch (tim) condition is declared. if they do match the tim condition is terminated. the 16 - byte expected trail trac e identifier is programmable. expected trail trace comparison is programmable (on or off). if multiframe alignment is disabled, expected trail trace comparison is disabled. immediately after a reset, the receive trail trace identifier is invalid. all compa risons between the receive trail trace identifier and expected trail trace identifier will match (a tim condition cannot occur) until after the first receive trail trace identifier update occurs. bit reordering changes the bit order of each byte. if bit re ordering is disabled, the incoming 8 - bit data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is output to the receive data storage with the msb in rtd[7] and the lsb in rtd[0] of the receive trace id data rtd[7:0]. if bit reordering is ena bled, the incoming 8 - bit data stream dt[1:8] is output to the receive data storage with the msb in rtd[0] and the lsb in rtd[7] of the receive trace id data rtd[7:0]. dt[1] is the first bit received from the incoming data stream. once all of the trail trac e processing has been completed, the 8 - bit parallel data stream is passed on to the receive data storage. 10.8.9 receive data storage the receive data storage block contains memory for 48 bytes of data, maintains data status information, and has controller circui try for reading and writing the memory. the receive data storage controller functions include filling the memory and maintaining the memory read and write pointers. the receive data storage accepts data and data status from the receive trace id processor, stores the data in memory, and maintains data status information. the data is read from the receive data storage via the microprocessor interface. the receive data storage contains the current trail trace identifier, the receive trail trace identifier, and the expected trail trace identifier. 10.9 feac controller 10.9.1 general description the feac controller demaps feac codewords from a ds3/e3 data stream in the receive direction and maps feac codewords into a ds3/e3 data stream in the transmit direction. the transmi t direction demaps feac codewords from a ds3/e3 data stream. the receive direction performs feac processing, and stores the codewords in the fifo using line timing. it removes the codewords from the fifo and outputs them to the microprocessor via the regis ter interface.
ds3170 ds3/e3 single - chip transceiver 103 of 230 the transmit direction inputs codewords from the microprocessor via the register interface and stores the codewords. it removes the codewords and performs feac processing. see figure 10-22 for the location of the feac controller in the block diagram figure 10- 22 . feac controller block diagram ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder 10.9.2 features ? programmable dual codeword output ? the transmit side can be programmed to output a single codeword ten times, one codeword ten times followed by a second codeword ten times, or a single codeword continuously. ? four codeword receive fifo ? fully independent transmit and receive paths ? fully independent line side and register side timing ? the fifo c an be read from or written to at the register interface side while all line side clocks and signals are inactive, and read from or written to at the line side while all register interface side clocks and signals are inactive. 10.9.3 functional description the bi ts in a code are received msb first, lsb last. when they are output serially, they are output msb first, lsb last. the bits in a code in an incoming signal are numbered in the order they are received, 1 (msb) to 6 (lsb). however, when a code is stored in a register, the msb is stored in the lowest numbered bit (0), and the lsb is stored in the highest numbered bit (5). this is to differentiate between a code in a register and the corresponding code in a signal. 10.9.3.1 transmit data storage the transmit data storag e block contains the registers for two feac codes (c{1:6]) and controller circuitry for reading and writing the memory. the transmit data storage receives data from the microprocessor interface , and stores the data in memory . the transmit feac processor re ads the data from the transmit data storage. 10.9.3.2 transmit feac processor the transmit feac processor accepts data from the transmit data storage performs feac processing. the feac codes are read from transmit data storage with the msb (c[1]) in tfca[0] or tfcb [0], and the lsb (c[6]) in tfca[5] or tfcb[5]. feac processing has four modes of operation (idle, single code, dual code, and continuous code). in idle mode, all ones are output on the outgoing feac data stream. in single code mode, the code from tfca[5:0 ] is inserted into a codeword ( figure 10-23 ), and sent ten consecutive times. once the ten codewords have been sent, all ones are output. in dual code mode, the code from tfca[5:0] is inserted into a cod eword, and sent ten consecutive times. then the code from tfcb[5:0] is inserted into a codeword, and sent ten consecutive times. once both codewords
ds3170 ds3/e3 single - chip transceiver 104 of 230 have both been sent ten times, all ones are output. in continuous mode, the code from tfca[5:0] is inserted into a codeword, and sent until the mode is changed 10.9.3.3 receive feac processor the receive feac processor accepts an incoming data line and extracts all overhead and performs feac code extraction , and idle detection. figure 10- 23 . feac codeword format cx - feac code receive/transmit order 1 0 c6 0 msb 1 lsb 16 1 1 1 1 1 1 1 c5 c4 c3 c2 c1 feac code extraction determines the codeword boundary by identifying the codeword sequence and extracts the feac code. a feac codeword is a repeating 16 - bit pattern (see figure 10-23 ). the codeword sequence is the pattern (0xxxxxx011111111) that contains each feac code (c[6:1]). each time slot is checked for a codeword sequence. once a codeword sequence is found, the feac code is checked. if the same feac c ode is received in three consecutive codewords without errors, the feac code detection indication is set, and the feac code is stored in the receive fifo with the msb (c[1]) in rff[0], and the lsb (c[6]) in rff[5]. the feac code detection indication is cle ared if two consecutively received feac codewords differ from the current feac codeword, or a feac idle condition is detected. idle detection detects a feac idle condition. a feac idle condition is declared if sixteen consecutive ones are received. the fea c idle condition is terminated when the feac code detection indication is set. 10.9.3.4 receive feac fifo the receive fifo block contains memory for four feac codes (c{1:6]) and controller circuitry for reading and writing the memory. the receive fifo controller fu nctions include filling the memory, tracking the memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow conditions. the receive fifo accepts data from the receive feac processor and stores the data in memory. the data is read from the receive fifo via the microprocessor interface. the receive fifo also outputs fifo fill status (empty) via the microprocessor interface. all operations are code based (six bits). the receive fifo is considered empty when i t does not contain any data. the receive fifo accepts data from the receive feac processor until full. if a feac code is received while full, the data is discarded and a fifo overflow condition is declared. if the receive fifo is read while the fifo is emp ty, the read is ignored. 10.10 line encoder/decoder 10.10.1 general description the b3zs/hdb3 decoder converts a bipolar signal to a unipolar signal in the receive direction. b3zs/hdb3 encoder converts a unipolar signal to a bipolar signal in the transmit direction. in the transmit direction, the encoder receives a unipolar signal, converts it to a bipolar signal, optionally performs zero suppression encoding, optionally inserts errors, and outputs the bipolar signals. in the receive direction, the decoder receives a b ipolar signal, monitors it for alarms and errors, optionally performs zero suppression decoding, and converts it to a unipolar signal. if the port line interface is configured for a unipolar mode, the bpv detector will count pulses on the rlcv pin. see figure 10-24 for the locations of the line encoder/ decorder block in the ds3170 device.
ds3170 ds3/e3 single - chip transceiver 105 of 230 figure 10- 24 . line encoder/decoder block diagram ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder 10.10.2 features ? performs bipolar to unipolar encoding and decoding ? converts a unipolar signal into an ami bipolar signal (pos data, and neg data) and vice versa. ? programmable zero suppression ? b3zs or hdb3 zero suppression encoding and decoding can be performed, or the bipolar data stream can be left as an ami encoded data stream. ? programmable receive zero suppression code format ? the signature of b3zs or hdb3 is selectable . ? generates and detects alarms and errors ? in the receive direction, detects los alarm condition bpv erro rs, and exz errors. in the transmit direction, errors can be inserted into the outgoing data stream. 10.10.3 b3zs/hdb3 encoder b3zs/hdb3 encoder performs unipolar to bipolar conversion and zero suppression encoding. unipolar to bipolar conversion converts the unip olar data stream into an ami bipolar data stream (pos and neg). in an ami bipolar data stream a zero is represented by a zero on both the pos and neg signals, and a one is represented by a one on a bipolar signal (pos or neg), and a zero on the other bipol ar signal (neg or pos). successive ones are represented by ones that are alternately output on the pos and neg signals. i.e., if a one is represented by a one on pos and a zero on neg, the next one will be represented by a one on neg and a zero on pos. zer o suppression encoding converts an ami bipolar data stream into a b3zs or hdb3 encoded bipolar data stream. a b3zs encoded bipolar signal is generated by inserting a b3zs signature into the bipolar data stream if both the pos and neg signals are zero for t hree consecutive clock periods. an hdb3 encoded bipolar signal is generated by inserting an hdb3 signature into the bipolar data stream if both the pos and neg signals are zero for four consecutive clock periods. zero suppression encoding can be disabled w hich will result in ami - coded data. error insertion is also performed. error insertion inserts bipolar violation (bpv) or excessive zero (exz) errors onto the bipolar signal. a bpv error will be inserted when three consecutive ones occur. an exz error wil l be inserted when three (or four) consecutive zeros on the bipolar signal occur by inhibiting the insertion of a b3zs (hdb3) signature. there will be at least one intervening pulse between consecutive bpv or exz errors. a single bpv or exz error inserted will be detected as a single bpv/exz error at the far - end, and will not cause any other type of error to be detected. for example, if a bpv error is inserted, the far - end should not also detect a data error. 10.10.4 transmit line interface the transmit line interf ace accepts a bipolar data stream from the b3zs/hdb3 encoder, performs error insertion, and transmits the bipolar data stream. error insertion inserts bpv or exz errors into the bipolar signal. when a bpv error is to be inserted, the transmit line interfac e waits for the next occurrence of three consecutive ones. the first bipolar one is generated according to the normal ami rules. the second bipolar one is generated by transmitting the same values on tpos and tneg
ds3170 ds3/e3 single - chip transceiver 106 of 230 as the values for the first one. the third bipolar one is generated according to the normal ami rules. when an exz error is to be inserted, the transmit line interface waits for the next occurrence of three (four) consecutive zeros on the bipolar signal, and inhibits the insertion of a b3zs (hdb3) signature. there must be at least one intervening one between consecutive bpv or exz errors. a single bpv or exz error inserted must be detected as a single bpv/exz error at the far - end, and not cause any other type of error to be detected. for example, i f a bpv error is inserted, the far - end should not also detect a data error. if a second error insertion request of a given type (bpv or exz) is initiated before a previous request has been completed, the second request will be ignored. the outgoing bipolar data stream consists of positive pulse data (tpos) and negative pulse data (tneg). tpos and tneg are updated on the rising edge of tlclk. 10.10.5 receive line interface the receive line interface receives a bipolar signal. the incoming bipolar data line consists of positive pulse data (rpos), negative pulse data (rneg), and clock (rlclk) signals. rpos and rneg are sampled on the rising edge of rlclk. the incoming bipolar signal is checked for a loss of signal (los) condition, and passed on to b3zs/hdb3 decoder. an los condition is declared if both rpos and rneg do not have any transitions for 192 clock cycles. the los condition is terminated after 192 clock cycles without any exz errors. note: when zero suppression (b3zs or hdb3) decoding is disabled, the los condi tion is cleared, and cannot be detected. 10.10.6 b3zs/hdb3 decoder the b3zs/hdb3 decoder receives a bipolar signal from the liu (or the rpos/rneg pins). the incoming bipolar signal is checked for a loss of signal (los) condition. an los condition is declared if b oth the positive pulse data and negative pulse data signals do not have any transitions for 192 clock cycles. the los condition is terminated after 192 clock cycles without any exz errors. b3zs/hdb3 decoder performs exz detection, zero suppression decoding , bpv detection, and bipolar to unipolar conversion. exz detection checks the bipolar data stream for excessive zeros (exz) errors. in b3zs mode, an exz error is declared whenever there is an occurrence of 3 or more zeros. in hdb3 mode, an exz error is dec lared whenever there is an occurrence of 4 or more zeros. exz errors are accumulated in the exz counter ( line.rexzcr register). zero - suppression decoding converts b3zs or hdb3 encoded bipolar data into an ami bipolar signal. in b3zs mode, the encoded bipol ar signal is checked for a b3zs signature. if a b3zs signature is found, it is replaced with three zeros. in hdb3 mode, the encoded bipolar signal is checked for an hdb3 signature. if an hdb3 signature is found, it is replaced with four zeros. the format of both an hdb3 signature and a b3zs signature is programmable. when line.rcr .rzsf = 0, the decoder will search for a zero followed by a bpv in b3zs mode, and in hdb3 mode it will search for two zeros followed b y a bpv. if line.rcr .rzsf = 1, the same criteria is applied with an additional requirement that the bpv must be the opposite polarity of the previous bpv. please refer to figure 10-25 and figure 10-26 . zero suppression decoding is also programmable (on or off). note: immediately after a reset or a los condition, the first b3zs/hdb3 signature to be detected will not depend upon the polarity of any bpv contained within the signature.
ds3170 ds3/e3 single - chip transceiver 107 of 230 figure 10- 25 . b3zs signatures rlclk rpos rneg (rx data) b3zs signature when line.rcr.rzsf = 0 v rlclk rpos rneg (rx data) v b3zs signature when line.rcr.rzsf = 1 v figure 10- 26 . hdb3 signatures rlclk rpos rneg (rx data) hdb3 signature when line.rcr.rzsf = 0 v rlclk rpos rneg (rx data) hdb3 signature when line.rcr.rzsf = 1 v v bpv detection check s the bipolar signal for bipolar violation (bpv) errors and e3 code violation (cv) errors. a bpv error is declared if two 1?s are detected on rxp or rxn without an intervening 1 on rxn or rxp, and the 1?s are not part of a b3zs/hdb3 signature, or when both rxp and rxn are a one. an e3 coding violation is declared if consecutive bpvs of the same polarity are detected (itu o.161 definition). e3 cvs are accumulated in the bpv counter ( line.rbpvcr register) if e3 cv detection has been enabled (applicable only i n hdb3 mode), otherwise, bpvs are accumulated in the bpv counter. if zero code suppression is disabled, the bpv counter will count all bipolar violations. the bpv counter will count pulses on the rlcv pin when the device is configured for unipolar mode. immediately after a reset (or datapath reset) or a los condition, a bpv will not be declared when the first valid one (rpos high and rneg low, or rpos low and rneg high) is received. bipolar to unipolar conversion converts the ami bipolar data into a unip olar signal by or?ing together the rxp and rxn signals.
ds3170 ds3/e3 single - chip transceiver 108 of 230 10.11 bert 10.11.1 general description the bert is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. it will gene rate and synchronize to pseudo - random patterns with a generation polynomial of the form x n + x y + 1, where n and y can take on values from 1 to 32 and to repetitive patterns of any length up to 32 bits. the transmit direction generates the programmable tes t pattern, and inserts the test pattern payload into the data stream. the receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern payload for the programmable test pattern. see figure 10-27 for the location of the bert block within the ds3170 device. figure 10- 27 . bert block diagram ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder 10.11.2 features ? programmable prbs pattern ? the pseudo random bit sequence ( prbs) polynomial (x n + x y + 1) and seed are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2 n - 1). ? programmable repetitive pattern ? the repetitive pattern length and pattern are programmable (the length n = 1 to 32 and pattern = 0 to 2 n - 1). ? 24- bit error count and 32- bit bit count registers ? programmable bit error insertion ? errors can be inserted individually, on a pin transition, or at a specific rate. the rate 1/10 n is programmable (n = 1 to 7). ? pattern synchronization at a 10 -3 ber ? pattern synchronization will be achieved even in the presence of a random bit error rate (ber) of 10 -3 . 10.11.3 configuration and monitoring set port.cr1 .bena = 1 to enable the bert. the bert must be enabled before the pattern is loaded for the pattern load operation to take affect. the following tables show how to configure the on - board bert to send and receive common patterns.
ds3170 ds3/e3 single - chip transceiver 109 of 230 table 10- 31 . pseudo - random pattern generation pattern type bert.pcr register bert. pcr bert. spr2 bert. spr1 bert.cr ptf[4:0] (hex) plf[4:0] (hex) pts qrss tpic, rpic 2 9 - 1 o.153 (511 type) 04 08 0 0 0x0408 0xffff 0xffff 0 2 11 - 1 o.152 and o.153 (2047 type) 08 0a 0 0 0x080a 0xffff 0xffff 0 2 15 -1 o.151 0d 0e 0 0 0x0d0e 0xffff 0xffff 1 2 20 - 1 o.153 10 13 0 0 0x1013 0xffff 0xffff 0 2 20 - 1 o.151 qrss 02 13 0 1 0x0253 0xffff 0xffff 0 2 23 - 1 o.151 11 16 0 0 0x1116 0xffff 0xffff 1 table 10- 32 . repetiti ve pattern generation pattern type bert.pcr register bert. pcr bert. spr2 bert. spr1 ptf[4:0] (hex) plf[4:0] (hex) pts qrss all 1s na 00 1 0 0x0020 0xffff 0xffff all 0s na 00 1 0 0x0020 0xffff 0xfffe alternating 1 s and 0s na 01 1 0 0x0021 0xffff 0xfffe double alternating and 0s na 03 1 0 0x0023 0xffff 0xfffc 3 in 24 na 17 1 0 0x0037 0xff20 0x0022 1 in 16 na 0f 1 0 0x002f 0xffff 0x0001 1 in 8 na 07 1 0 0x0027 0xffff 0xff01 1 in 4 na 03 1 0 0x0023 0xffff 0xfff1 after configuring these bits, the pattern must be loaded into the bert. this is accomplished via a zero -to - one transition on bert.cr .tnpl and bert.cr .rnpl monitoring the bert requires reading the bert.sr register which contains the bit error count (bec) bit and the out of synchronization (oos) bit. the bec bit will be one when the bit error counter is one or more. the oos will be one whe n the receive pattern generator is not synchronized to the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64 bit window. the receive bert bit count register ( bert.rbcr1 ) and the receive bert bit error count register ( bert.rbecr1 ) will be updated upon the reception of a performance monitor update signal (e.g. bert.cr.lpmu). this signal will update the registers with the values of t he counter since the last update and will reset the counters. please see section 10.4.5 for more details of the pmu. 10.11.4 receive pattern detection since the receive bert is always enabled, it can be used as an off - l ine monitor. the receive bert receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. the receive pattern generator is a 32 - bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1) , the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n a nd y are individually programmable (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output will be forced to one if the next 14 bits are all zeros. qrss is program mable (on or off). for prbs and qrss patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. depending on the type of pattern programmed, pattern detection performs either prbs synchronization or repetitive pattern synchronization. 10.11.4.1 receive prbs synchronization prbs synchronization synchronizes the receive pattern generator to the incoming prbs or qrss pattern. the receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
ds3170 ds3/e3 single - chip transceiver 110 of 230 then c hecking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64 - bit window do not match the receive pattern generator, automatic pattern resynchronization is initi ated. automatic pattern resynchronization can be disabled. refer to figure 10-28 for the prbs synchronization diagram. figure 10- 28 . prbs synchronization s tate diagram sync load verify 1 bit error 32 bits loaded 32 bits without errors 6 of 64 bits with errors 10.11.4.2 receive repetitive pattern synchronization repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. the receive pattern generator is synchronized by searching each incoming data stre am bit position for the repetitive pattern, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64 - bit window do not match the receive prbs patt ern generator, automatic pattern resynchronization is initiated. automatic pattern resynchronization can be disabled. refer to figure 10-29 for the repetitive pattern synchronization state diagram.
ds3170 ds3/e3 single - chip transceiver 111 of 230 fig ure 10- 29 . repetitive pattern synchronization state diagram sync match verify 1 bit error pattern matches 32 bits without errors 6 of 64 bits with errors 10.11.4.3 receive pattern monitoring receive pattern monitoring monitors the incoming data stream for both an oos condition and bit errors and counts the incoming bits. an out of synchronization (oos) condition is declared when the synchronization state machine is not in the ?sync? state. an oos condition is terminated when the synchronization state machine is in the ?sync? state. bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. if they do not match, a bit error is declared, and the bit error and bit counts are incremented. if they match, only the bit count is incremented . the bit count and bit erro r count are not incremented when an oos condition exists . 10.11.5 transmit pattern generation pattern generation generates the outgoing test pattern, and passes it onto error insertion. the transmit pattern generator is a 32 - bit shift register that shifts data fr om the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1) , the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output will be forced to one if t he next 14 bits are all zeros. qrss is programmable (on or off). for prbs and qrss patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. when a new pattern is loaded, the pattern generator is loaded with a seed/pattern value befo re pattern generation starts. the seed/pattern value is programmable (0 ? 2 n - 1). 10.11.5.1 transmit error insertion error insertion inserts errors into the outgoing pattern data stream. errors are inserted one at a time or at a rate of one out of every 10 n bits. the value of n is programmable (1 to 7 or off) . single bit error insertion can be initiated from the microprocessor interface, or by the manual error insertion input (tmei). the method of single error insertion is programmable (register or input). if patt ern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. pattern inversion is programmable (on or off).
ds3170 ds3/e3 single - chip transceiver 112 of 230 10.12 liu ? line interface unit 10.12.1 general description the line interface units (lius) perform the functions necessary for interfacing at the physical layer to ds3 or e3 lines. the liu has independent receive and transmit paths and a built - in jitter attenuator. see figure 10-30 for the location within the ds3170 device of the liu. figure 10- 30 . liu functional diagram ds3/e3 transmit liu ieee p1149.1 jtag test access port microprocessor interface hdlc feac llb dlb ds3 / e3 transmit formatter ds3 / e3 receive framer trail trace buffer ds3/e3 receive liu tais tua1 clock rate adapter tx bert rx bert plb alb ua1 gen b3zs/ hdb3 encoder b3zs/ hdb3 decoder 10.12.2 features ? performs receive clock/data recovery and transmit waveshaping ? jitter attenuators can be placed in either the receive or transmit paths ? interfaces to 75 ? coaxial cable at lengths up to 380 meters (ds3), 440 meters (e3) ? use 1:2 transformers on tx and rx ? requires minimal external components ? local and remote loopbacks 10.12.2.1 transmitter ? gapped clock capable up to 52mhz ? wide 50 20% transmit clock duty cycle ? cloc k inversion for glueless interfacing ? unframed all - ones generator (e3 ais) ? line build - out (lbo) control ? tri - state line driver outputs support protection switching applications ? per - channel power - down control ? output driver monitor 10.12.2.2 receiver ? agc/equalizer block handles from 0 to 15db of cable loss ? loss -of - lock (lol) pll status indication ? interfaces directly to a dsx monitor signal (~20db flat loss) using built - in preamp ? digital and analog loss -of - signal (los) detectors (ansi t1.231 and itu g.775) ? clock inversion for glueless interfacing ? per - channel power - down control 10.12.3 detailed description the receiver performs clock and data recovery from an alternate mark inversion (ami) coded signal or a b3zs - or hdb3 - coded ami signal and monitors for loss of the incoming signal . the transmitter drives standard pulse- shape
ds3170 ds3/e3 single - chip transceiver 113 of 230 waveforms onto 75 ? coaxial cable. refer to figure 10- 31 for a detailed functional block diagram of the ds3/e3 liu. the jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path, or be disabled. the ds3/e3 liu conforms to the telecommunications standards listed in table 5 -1 . figur e 2 -1 shows the external components required for proper operation. figure 10- 31 . ds3/e3 liu block diagram analog local loopback preamp clock & data recovery line driver waveshaping rxpn rxnn txpn txnn power supply squelch jitter attenuator (can be placed in either the receive path or the transmit path) driver monitor vdd vss automatic gain control + adaptive equalizer alos clock rate adapter refclk to b3zs/hdb3 decoder from b3zs/hdb3 encoder from ds3/e3 line to ds3/e3 line 10.12.4 transmitter 10.12.4.1 transmit clock the clock used in the liu transmitter is typically based on either the clad clock or tclki, selected by the cladc bit in port.cr3 . 10.12.4.2 waveshaping, line build - out, line driver the waveshaping block converts the transmit clock, positive data, and negative data signals into a single ami signal with the waveshape requi red for interfacing to ds3/e3 lines. table 16-7 through table 16-9 and figure 16-11 (ac timing sectio n) show the waveform template specifications and test parameters. because ds3 signals must meet the waveform templates at the cross - connect through any cable length from 0 to 450ft, the waveshaping circuitry includes a selectable lbo feature. for cable len gths of 225ft or greater, the tlbo configuration bit ( port.cr2 .tlbo) should be low. when tlbo is low, output pulses are driven onto the coaxial cable without any preattenuation. for cable lengths less than 225ft, tlbo should be high to enable the lbo circu itry. when tlbo is high, pulses are preattenuated by the lbo circuitry before being driven onto the coaxial cable. the lbo circuitry provides attenuation that mimics the attenuation of 225ft of coaxial cable. the transmitter line driver can be disabled and the txp and txn outputs tri - stated by asserting the lts configuration bit ( port.cr2 .lts). powering down the transmitter through the tpd configuration bit (cpu bus mode) also tri - states the txp and txn outputs.
ds3170 ds3/e3 single - chip transceiver 114 of 230 10.12.4.3 interfacing to the line the transmitter int erfaces to the outgoing ds3/e3 coaxial cable (75 ? ) through a 2:1 step - down transformer connected to the txp and txn pins. figure 2 -1 shows the arrangement of the transformer and other recommended interface components. table 10-33 specifies the required characteristics of the transformer. 10.12.4.4 transmit driver monitor if the transmit driver monitor detects a faulty transmitter, it sets the port.sr .tdm status bi t. when the transmitter is tri - stated, the transmit driver monitor is also disabled. the transmitter is declared to be faulty when the transmitter outputs see a load of less than ~25 ? . 10.12.4.5 transmitter power - down to minimize power consumption when the transm itter is not being used, assert the port.cr1 .pd configuration bit. when the transmitter is powered down, the txp and txn pins are put in a high - impedance state and the transmit amplifiers are powered down. 10.12.4.6 transmitter jitter generation (intrinsic) the transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter attenuator enabled. 10.12.4.7 transmitter jitter transfer without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. with the jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer requirements of all applicable telecommunication standards. see table 5 -1 . 10.12.5 receiver 10.12.5.1 interfac ing to the line the receiver can be transformer - coupled or capacitor - coupled to the line. typically, the receiver interfaces to the incoming coaxial cable (75 ? ) through a 1:2 step - up transformer. figure 2 -1 shows the arrangement of the transformer and other recommended interface components. table 10-33 specifies the required characteristics of the transformer. figure 10-31 shows a general overview of the liu block. the receiver expects the incoming signal to be in b3zs - or hdb3 - coded ami format. table 10- 33 . transformer characteristics parameter value turns ratio 1:2ct 2% bandwidth 75 ? 0.250mhz to 500mhz (typ) primary inductance 19 h (min) leakage inductance 0.12 h (max) interwinding capacitance 10pf (max) isolation voltage 1500v rms (min)
ds3170 ds3/e3 single - chip transceiver 115 of 230 table 10- 34 . re commended transformers manufacturer part temp range pin - package/ schematic ocl primary ( h) (min) l l ( h) (max) bandwidth 75 ? (mhz) pulse engineering pe-65968 0c to +70c 6 smt ls - 1/c 19 0.06 0.250 to 500 pulse engineering pe-65969 0c to +70c 6 thru - hole lc- 1/c 19 0.06 0.250 to 500 halo electronics tg07 - 0206ns 0c to +70c 6 smt smd/b 19 0.06 0.250 to 500 halo electronics td07 - 0206ne 0c to +70c 6 dip dip/b 19 0.06 0.250 to 500 note: table subject to change. industrial temperature range and mul tiport transformers are also available. contact the manufacturers for details at www.pulseeng.com and www.haloelectronics.com . 10.12.5.2 optional preamp the receiver can be u sed in monitoring applications, which typically have series resistors with a resistive loss of approximately 20db. when the port.cr2 .rmon bit is high, the receiver compensates for this resistive loss by applying fla t gain to the incoming signal before sending the signal to the agc/equalizer block. 10.12.5.3 automatic gain control (agc) and adaptive equalizer. the agc circuitry applies flat (frequency independent) gain to the incoming signal to compensate for flat losses in the transmission channel and variations in transmission power. since the incoming signal also experiences frequency - dependent losses as it passes through the coaxial cable, the adaptive equalizer circuitry applies frequency - dependent gain to offset line lo sses and restore the signal. the agc/equalizer circuitry automatically adapts to coaxial cable losses from 0 to 15db, which translates into 0 to 380 meters (ds3) or 0 to 440 meters (e3) of coaxial cable (at&t 734a or equivalent). the agc and the equalizer work simultaneously but independently to supply a signal of nominal amplitude and pulse shape to the clock and data recovery block. the agc/equalizer block automatically handles direct (0 meters) monitoring of the transmitter output signal. 10.12.5.4 clock and dat a recovery (cdr) the cdr block takes the amplified, equalized signal from the agc/equalizer block and produces a separate clock, positive data, and negative data signals. the cdr requires a master clock. the master clock is derived from refclk. the receiv e clock is locked using a clock recovery pll. the status of the pll lock is indicated in the rlol ( port.sr ) status bit. the receive loss -of - lock status bit (rlol) is set when the differ ence between the recovered clock frequency and the master clock frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. a change of state of the port.sr .rlol status bit can cause an interrupt on the int pin if enabled to do so by the port.srie .rlolie inter rupt - enable bit. note that if the master clock is not present, or the master clock is high and tclk is not present, rlol is not set. 10.12.5.5 loss -of - signal (los) detector the receiver contains analog and digital los detectors. the analog los detector resides in the agc/equalizer block. if the incoming signal level is less than a signal level approximately 24db below nominal, analog los (alos) is declared. the alos signal cannot be directly examined, but when alos occurs the agc/equalizer mutes the recovered data, forcing all zeros out of the data recovery circuitry and causing digital los (dlos). dlos is determined by the line decoder block (see section 10.10.4 ) and indicated by the los status bit ( line.rsr . alos clears when the incoming signal level is greater than or equal to a signal level approximately 18db below nominal. los). for e3 los assertion:
ds3170 ds3/e3 single - chip transceiver 116 of 230 the alos detector in the agc/equalizer block detects that the incoming signa l is less than or equal to a signal level approximately 24db below nominal, and mutes the data coming out of the clock and data recovery block. (24db below nominal in the ?tolerance range? of g.775, where los may or may not be declared.) for e3 los clear: the alos detector in the agc/equalizer block detects that the incoming signal is greater than or equal to a signal level approximately 18db below nominal, and enables data to come out of the cdr block. (18db is in the ?tolerance range? of g.775, where los may or may not be declared.) 10.12.5.6 receiver power - down to minimize power consumption when the receiver is not being used, write a one to the port.cr1 .pd bit. when the receiver is powered down, the rclko pin is tri - stated. in addition, the rxp and rxn pins become high impedance. 10.12.5.7 receiver jitter tolerance. the receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in table 5 -1 . see figure 10-32 . figure 10- 32 . receiver jitter tolerance 10 100 1k 10k 100k 1m 60k 22.3k 2.3k 669 0.1 1.0 10 300k 800k 300 30 0.1 0.15 0.3 10 5 1.5 e3 g.823 ds3 gr-499 cat ii ds3 gr-499 cat i ds317 0 jitter tolerance 15 sts-1 gr253 frequency (hz) jitter tolerance (ui p-p )
ds3170 ds3/e3 single - chip transceiver 117 of 230 11 overall register map the register addresses of the global, test and the port are concatenated to cover the address range of 000 to 7f f. the address map requires 9 bits of address, adr[8:0]. the register banks that are not marked with an ?x? are not writeable and read back all zeroes. bits that are underlined unused bits and registers mark ed with ? ? ? are ignored when written to, and return zero when read. are read - only; all other bits are read- write. configuration registers can be written to and read from during a data path reset ( drst low, and rst high). however, all changes to these registers will be ignored during the data path res et. as a result, all initiating action requiring a ?0 to 1? transition must be re - initiated after the data path reset is released. all counters saturate at their maximum count. a counter register is updated by asserting (low to high transition) the perform ance monitoring update signal (pmu). during the counter register update process, the performance monitoring status signal (pms) will be deasserted. the counter register update process consists of loading the counter register with the current count, resetti ng the counter, forcing the zero count status indication low for one clock period , and then asserting pms. no events shall be missed during an update procedure. a latched bit is set when the associated event occurs, and remains set until it is cleared. onc e cleared, a latched bit will not be set again until the associated event reoccurs (goes away and comes back). a latched on change bit is a latched bit that is set when the event occurs, and when it goes away. a latched status bit can be cleared using clea r on read or clear on write techniques, selectable by the gl.cr1 .lsbcre bit . when clear on write is selected, the latched bits in a latched status register will be cleared after the register is read from. if the devic e is configured for 16 - bit mode, all 16 latched status bits will be cleared. if the device is configured for 8 -bit mode, only the 8 bits being accessed will be cleared. when clear on write is selected, the latched bits in a latched status register will be cleared when a logic 1 is written to that bit position. for example, writing a ffffh to a 16 - bit latched status register will clear any latched status bit, whereas writing a 0001h will only clear latched bit 0 of the latched status register. reserved bits and registers are implemented in a different mode. reserved configuration bits and registers can be written and read, however they will not affect the operation of the current mode. reserved status bits will be zero. reserved latched status bits cannot be set, however, they may remain set or get set during a mode change. reserved interrupt enable bits can be written and read, and can cause an interrupt if the associated latched status bit is set . reserved counter registers and the associated counter will re tain the values held before a mode change, however, the associated counter cannot be incremented. a performance monitor update will operate normally. if the data path reset is set during or after a mode change, the latched status bits and counter registers (with the associated counters) will be automatically cleared. if the data path reset is not used, then the latched status bits must be cleared via the register interface in the normal manner. a nd, the counter registers must be cleared by performing two pe rformance monitor updates. the first to clear the associated counter, and load the current count into the counter register, and the second to clear the counter register. the term ?global? is used to make the register names compatible with the mult - port ver sions (ds3174, ds3173, ds3172, ds3171) of this device. note: the rdy signal will not go active if the user attempts to read or write unused registers not assigned to any design blocks. the rdy signal will go active if the user writes or reads reserved regi sters or unused registers within design blocks. table 11- 1 . register address map address offset description 000 - 01f global registers 020 ? 03f unused 040 - 05f port control registers 060 ? 07f bert 080 ? 08b unused
ds3170 ds3/e3 single - chip transceiver 118 of 230 address offset description 08c ? 08f b3zs/hdb3 transmit line encoder 090 ? 09f b3zs/hdb3 receive line decoder 0a0 ? 0af hdlc transmit 0b0 ? 0bf hdlc receive 0c0 ? 0cf feac transmit 0d0 ? 0df feac receive 0e0 ? 0e7 unused 0e8 ? 0ef trail trace transmit 0f0 ? 0f f trail trace receive 100 ? 117 unused 118 ? 11f ds3/e3 framer transmit 120 ? 13f ds3/e3 framer receive 140 ? 17f unused 180 ? 19f test registers 1a0 ? 1ff unused
ds3170 ds3/e3 single - chip transceiver 119 of 230 12 register maps and de scriptions 12.1 registers bit maps note: in 8 - bit mode, register bi ts[15:8] correspond to the upper byte, and register bits[7:0] correspond to the lower byte. for example, address 001h is the upper byte (bits [15:8]) and address 000h is the lower byte (bits [7:0]) for register gl.idr in 8 - bit mode. all registers listed, i ncluding those designated unused and reserved, will cause the rdy signal to go low when written to or read from. the ? ? ? designation indicates that the bit is not assigned. 12.1.1 global register bit map table 12- 1 . global register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 000 000 r gl.idr id7 id6 id5 id4 id3 id2 id1 00 1 id0 id15 id14 id13 id12 id11 id10 id9 002 id8 002 rw gl.cr1 tmei meims gpm1 gpm0 pmu lsbcre rstdp rst 003 -- intm -- -- -- -- -- -- 004 004 rw gl.cr2 -- -- -- -- clad2 clad 1 clad0 -- 005 -- -- -- -- g8krs1 g8krs0 g8k0s g8kis 006- 008 006 - unused -- -- -- -- -- -- -- -- 009 -- -- -- -- -- -- -- -- 00a 00a rw gl.giocr gpio4s1 gpio4s0 gpio3s1 gpio3s0 gpio2s1 gpio2s0 gpio1s1 gp io1s0 00b gpio8s1 gpio8s0 gpio7s1 gpio7s0 gpio6s1 gpio6s0 gpio5s1 gpio5s0 00c 00c unused -- -- -- -- -- -- -- -- 00d -- -- -- -- -- -- -- -- 010 010 r gl.isr -- pisr -- -- gsr 011 -- -- -- -- -- -- - - -- 012 012 rw gl.isrie pisrie -- -- -- gsrie 013 014 014 r gl.sr -- -- -- -- -- -- clol 015 gpms -- -- -- -- -- -- -- -- 016 016 rl gl.srl -- -- -- 8krefl cladl onesl cloll 017 gpmsl -- -- -- -- -- -- -- -- 018 018 r gl.srie -- -- -- -- -- onesie clolie gpmsie 019 -- -- -- -- -- -- -- -- 01a 01a unused -- -- -- -- - - -- -- -- 01b -- -- -- -- -- -- -- -- 01c 01c gl.giorr r gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 01d gpio1 -- -- -- -- -- -- -- -- 01e 01e unused -- -- -- -- -- -- -- -- 01f -- -- -- -- -- -- -- -- table 12- 2 . port register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
ds3170 ds3/e3 single - chip transceiver 120 of 230 address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 040 040 rw port.cr1 tmei meim -- pmum pmu pd rstdp rst 0 41 res pais2 pais1 pais0 lais1 lais0 bena res 042 0 42 rw port.cr2 res res fm2 fm1 fm0 res res res 0 43 tlen tts rmon tlbo res lm2 lm1 lm0 044 044 rw port.cr3 p8krs1 p8krs0 p8kref loopt cladc rfts tfts tlts 045 -- -- rclks rsofos res tclks tsofos res 046 0 46 rw port.cr4 gpiob3 gpiob2 gpiob1 gpiob0 gpioa3 gpioa2 gpioa1 gpioa0 0 47 -- -- -- -- res lbm2 lbm1 lbm0 048 048 unused -- -- -- -- -- -- -- -- 049 -- -- -- -- -- -- -- -- 04a 04a rw port.inv1 tohi tohcki tsofii tnegi tdati tlcki tckoi tckii 04b res res -- tsofoi res tseri tohsi tohei 04c 0 4c rw port.inv2 rohi rohcki -- rnegi rposi rlcki rclkoi -- 0 4d -- res res rsofoi -- rseri rohsi -- 04e 04e unused -- -- -- -- -- -- -- -- 04f -- -- -- -- -- -- -- -- 050 050 r port.isr ttsr fsr hsr res bsr res res 051 fmsr -- -- -- -- -- -- psr 052 lcsr 052 r port.sr -- -- -- -- -- tdm rlol 053 pms -- -- -- -- -- -- -- -- 054 054 rl port.srl rlclkl tclkil -- -- -- tdml rloll pmsl 055 -- -- -- -- -- -- -- -- 056 056 rw port.srie -- -- -- -- -- tdmie rlolie pmsie 057 -- -- -- -- -- -- -- -- 058- 05e 0 58 - unuse d -- -- -- -- -- -- -- -- 0 5f -- -- -- -- -- -- -- -- table 12- 3 . bert register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 b it 11 bit 10 bit 9 bit 8 060 0 60 rw bert.cr pmum lpmu rnpl rpic mpr aprd tnpl tpic 0 61 -- -- -- -- -- -- -- -- 062 062 rw bert.pcr -- qrss pts plf4 plf3 plf2 plf1 plf0 063 -- -- -- ptf4 ptf3 ptf2 ptf1 ptf0 064 064 rw bert.spr1 bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 065 bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 066 066 rw bert.spr2 bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 067 bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 068 0 68 rw bert.teicr -- -- teir2 teir1 teir0 bei tsei meims 0 69 -- -- -- -- -- -- -- -- 06a 0 6a unused -- -- -- -- -- -- -- -- 06b -- -- -- -- -- -- -- -- 06c 0 6c r bert.sr -- -- -- -- -- pms bec 0 6d oos -- -- -- -- -- -- -- -- 06e 0 6e rl bert.srl -- -- -- - - pmsl bel becl 0 6f oosl -- -- -- -- -- -- -- -- 070 0 70 rw bert.srie -- -- -- -- pmsie beie becie oosie 0 71 -- -- -- -- -- -- -- -- 072 072 unused -- -- -- -- -- -- -- -- 073 -- -- -- -- -- -- -- - -
ds3170 ds3/e3 single - chip transceiver 121 of 230 address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 b it 11 bit 10 bit 9 bit 8 074 074 r bert.rbecr1 bec7 bec6 bec5 bec4 bec3 bec2 bec1 075 bec0 bec15 bec14 bec13 bec12 bec11 bec10 bec9 076 bec8 0 76 r bert.rbecr2 bec23 bec22 bec21 bec2 0 bec19 bec18 bec17 0 77 bec16 -- -- -- -- -- -- -- -- 078 0 78 r bert.rbcr1 bc7 bc6 bc5 bc4 bc3 bc2 bc1 0 79 bc0 bc15 bc14 bc13 bc12 bc11 bc10 bc9 07a bc8 07a r bert.rbcr2 bc23 bc22 bc21 bc20 bc19 bc18 bc17 07b bc16 bc31 bc30 bc29 bc28 bc27 bc26 bc25 07c- 07e bc24 0 7c unused -- -- -- -- -- -- -- -- 0 7f -- -- -- -- -- -- -- -- table 12- 4 . line register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 08c 08c rw line.tcr -- -- -- tzsd exzi bpvi tsei meims 08d -- - - -- -- -- -- -- -- 08e 08e unused -- -- -- -- -- -- -- -- 08f -- -- -- -- -- -- -- -- 090 090 rw line.rcr -- -- -- -- e3cve rezsf rdzsf rzsd 091 -- -- -- -- -- -- -- -- 092 092 unused -- -- -- -- -- -- -- -- 093 -- -- -- -- -- -- -- -- 094 094 r line.rsr -- -- -- -- -- exzc bpvc 095 los -- -- -- -- -- -- -- -- 096 096 rl line.rsrl -- -- zscdl exzl exzc l bpvl bpvcl 097 losl -- -- -- -- -- -- -- -- 098 098 rw line.rsrie -- -- zscdie exzie exzcie bpvie bpvcie losie 099 -- -- -- -- -- -- -- -- 09a 09a unused -- -- -- -- -- -- -- -- 09b -- -- -- -- -- -- -- -- 09c 09c r line.rbpvcr bpv7 bpv6 bpv5 bpv4 bpv3 bpv2 bpv1 09d bpv0 bpv15 bpv14 bpv13 bpv12 bpv11 bpv10 bpv9 09e bpv8 09e r line.rexzcr e xz7 exz6 exz5 exz4 exz3 exz2 exz1 09f exz0 exz15 exz14 exz13 exz12 exz11 exz10 exz9 exz8 12.1.2 hdlc register bit map table 12- 5 . hdlc register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0a0 0a0 rw hdlc.tcr -- tpsd tfei tifv tbre tdie tfpd tfrst 0a1 -- -- -- tdal4 tdal3 tdal2 tdal1 tdal0 0a2 0a2 rw hdlc.tfdr -- -- -- -- -- -- -- tdpe 0a3 tfd7 tfd6 tfd5 tfd4 tfd3 tfd2 tfd1 tfd0 0a4 0a4 r hdlc.tsr -- -- -- -- -- tff tfe 0a5 thda -- -- tffl5 tffl4 tffl3 tffl2 tffl1 0a6 tffl0 0a6 rl hdlc.tsrl -- -- tfol tful -- tpel tfel 0a7 thdal -- -- -- -- -- -- -- -- 0a8 0a8 rw hdlc.tsrie -- -- tfoie tfuie tpeie -- tfeie thdaie 0 a9 -- -- -- -- -- -- -- --
ds3170 ds3/e3 single - chip transceiver 122 of 230 address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0aa - 0ae 0aa unused -- -- -- -- -- -- -- -- 0af -- -- -- -- -- -- -- -- 0b0 0b0 rw hdlc.rcr -- -- -- -- rbre rdie rfpd rfrst 0b1 -- -- -- rdal4 rdal3 rdal2 rdal1 rdal0 0b2 0b2 unused -- -- -- -- -- -- -- -- 0b3 -- -- -- -- -- -- -- -- 0b4 0b4 r hdlc.rsr -- -- -- -- -- rff rfe 0b5 rhda -- -- -- -- -- -- -- -- 0b6 0b6 rl hdlc.rsrl -- rfol -- rpel rpsl -- rffl 0b7 rhdal -- -- -- -- -- -- -- -- 0b8 0b8 rw hdlc.rsrie rfoie -- -- rpeie rpsie rffie -- rhdaie 0b9 -- -- -- -- -- -- -- -- 0ba 0ba unused -- -- -- -- -- -- -- -- 0bb -- -- -- -- -- -- -- -- 0bc 0bc r hdlc.rfdr -- -- -- -- rps2 rps1 rps0 0bd rfdv rfd7 rfd6 rfd5 rfd4 rfd3 rfd2 rfd1 0be rfd0 0be unused -- -- -- -- -- -- -- -- 0bf -- -- -- -- -- -- -- -- tab le 12- 6 . feac register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0c0 0c0 rw feac.tcr -- -- -- -- -- tfcl tfs1 tfs0 0c1 -- -- -- -- -- -- -- -- 0c2 0c2 rw feac.tfdr -- -- tfca5 tfca4 tfca3 tfca2 tfca1 tfca0 0c3 -- -- tfcb5 tfcb4 tfcb3 tfcb2 tfcb1 tfcb0 0c4 0c 4 r feac.tsr -- -- -- -- -- -- -- 0c5 tfi -- -- -- -- -- -- -- -- 0c6 0c6 rl feac.tsrl -- -- -- -- -- -- -- 0c7 tfil -- -- -- -- -- -- -- -- 0c8 0c8 rw feac.tsrie -- -- -- -- -- -- -- tfiie 0c9 -- -- -- -- -- -- -- -- 0ca - 0ce 0ca unused -- -- -- -- -- -- -- -- 0cf -- -- -- -- -- -- -- -- 0d0 0d0 rw feac.rcr -- -- -- -- -- -- -- rfr 0d1 -- -- -- -- -- -- -- -- 0d2 0d2 unused -- -- -- -- -- -- -- -- 0d3 -- -- -- -- -- -- -- -- 0d4 0d4 r feac.rsr -- -- -- -- -- rffe rfcd 0d5 rfi -- -- -- -- -- -- -- -- 0d6 0d6 rl feac.rsrl -- -- -- -- -- rffol rfcdl 0d7 rfil -- -- -- -- -- -- -- -- 0d8 0d8 rw feac.rsrie -- -- -- -- -- rffoie rfcdie rfiie 0d9 -- -- -- -- -- -- -- -- 0da 0da unused -- -- -- -- -- -- -- -- 0db -- -- -- -- -- -- -- -- 0dc 0dc r feac.rfdr -- rffi rff5 rff4 rff3 rff2 rff1 0dd rff0 -- -- -- -- -- -- -- -- 0de 0de unused -- -- -- -- -- - - -- -- 0df -- -- -- -- -- -- -- --
ds3170 ds3/e3 single - chip transceiver 123 of 230 table 12- 7 . trail trace register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0e8 0e8 rw tt.tcr -- -- -- reserved tmad tidle tdie tbre 0e9 -- -- -- -- -- -- -- -- 0ea 0ea r tt.ttiar -- -- reserved reserved ttia3 ttia2 ttia1 ttia0 0eb -- -- -- -- -- -- -- -- 0ec 0ec r tt.tir ttd7 ttd6 ttd5 ttd4 ttd3 ttd2 ttd1 ttd0 0ed -- -- -- -- -- -- -- -- 0ee 0ee unused -- -- -- -- -- -- -- -- 0ef -- -- -- -- -- -- -- -- 0f0 0f0 rw tt.rcr -- -- reserved reserved rmad retcd rdie rbre 0f1 -- -- -- -- -- -- -- -- 0f2 0f2 r tt.rtiar -- -- reserved reserved rtia3 rtia2 rtia1 rtia0 0f3 -- -- reserved reserved etia3 etia2 etia1 etia0 0f4 0f4 r tt.rsr -- -- -- -- -- rtim rtiu 0f5 ridl -- -- -- -- -- -- -- -- 0f6 0f6 rl tt.rsrl -- -- -- -- rticl rtiml rtiul 0f7 ridll -- -- -- -- -- -- -- -- 0f8 0f8 rw tt.rsrie -- -- -- -- rticie rtimie rtiuie ridlie 0f9 -- -- -- -- -- -- -- -- 0fa 0fa unused -- -- -- -- -- -- -- -- 0fb -- -- -- -- -- -- -- -- 0fc 0fc r tt.rir rtd7 rtd6 rtd5 rtd4 rtd3 rtd2 rtd1 0fd rtd0 -- -- -- -- -- -- -- -- 0fe 0fe r tt.eir etd7 etd6 etd5 etd4 etd3 etd2 etd1 etd0 0ff -- -- -- -- -- -- -- -- 100 - 116 100 - 1117 reserv ed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12.1.3 t3 register bit map table 12- 8 . t3 register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 118 118 rw t3.tcr -- -- tfebe afebed trdi ardid tfgd tais 119 -- -- -- pbge tidle cbge -- -- 11a 11a rw t3.teir reserved cpeie pei feic1 feic0 fei tsei meims 11b -- -- -- -- ccpeie cpei cfbeie fbei 11c - 11e 11c reserved -- -- -- -- -- -- -- -- 11f -- -- -- -- -- -- -- -- 120 120 rw t3.rcr raile raild raiod raiad romd lip1 lip0 frsy nc 121 reserved covhd maod mdaisi aaisd ecc fecc1 fecc0 122 122 reserved -- -- -- -- -- -- -- -- 123 -- -- -- -- -- -- -- -- 124 124 r t3.rsr1 oomf -- sef lof rai ais oof 125 los reserved -- reserved reserved t3fm aic idle 126 rua1 126 r t3.rsr2 -- -- -- -- cpec fbec pec 127 fec -- -- -- -- -- -- -- -- 128 128 rl t3.rsrl1 oomfl sefl cofal lofl rail aisl oofl 129 lo sl reserved reserved reserved reserved t3fml aicl idlel rua1l
ds3170 ds3/e3 single - chip transceiver 124 of 230 address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 12a 12a rl t3.rsrl2 -- -- -- -- cpecl fbecl pecl 12b fecl -- -- -- -- cpel fbel pel 12c fel 12c rw t3.r srie1 oomfie sefie cofaie lofie raiie aisie oofie losie 12d reserved reserved reserved reserved t3fmie aicie idleie rua1ie 12e 12e rw t3.rsrie2 -- -- -- -- cpecie fbecie pecie fecie 12f -- -- -- -- cpeie fbeie peie feie 130 - 132 130 reserved -- -- -- -- -- -- -- -- 133 -- -- -- -- -- -- -- -- 134 134 r t3.rfecr fe7 fe6 fe5 fe4 fe3 fe2 fe1 135 fe0 fe15 fe14 fe13 fe12 fe11 fe10 fe9 136 fe8 136 r t3.rpecr pe7 pe6 pe5 pe4 pe3 pe2 pe1 137 pe0 pe15 pe14 pe13 pe12 pe11 pe10 pe9 138 pe8 138 r t3.rfbecr fbe 7 fbe 6 fbe 5 fbe 4 fbe 3 fbe 2 fbe 1 fbe 0 139 fb e fbe 15 fbe 14 fbe 13 fbe 12 fbe 11 fbe 9 10 fbe 8 13a 13a r t3.rcpecr cpe7 cpe6 cpe5 cpe4 cpe3 cpe2 cpe1 13b cpe0 cpe15 cpe14 cpe13 cpe12 cpe11 cpe10 cpe9 13c - 13e cpe8 13c unused -- -- -- -- -- -- -- -- 13f -- -- -- -- -- -- -- -- 12.1.4 e3 g.751 register bit map table 12- 9 . e3 g.751 register bit map address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 118 118 rw e3g751.tcr -- -- reserved reserved tabc1 tabc0 tfgd tais 119 reserved -- -- reserved reserved reserved tnbc1 tnbc0 11a 11a rw e3g751 .teir reserved reserved reserved feic1 feic0 fei tsei meims 11b -- -- -- -- reserved reserved reserved reserved 11c- 11e 11c reserved -- -- -- -- -- -- -- -- 11f -- -- -- -- -- -- -- -- 120 120 rw e3g751.rcr raile raild raiod raiad romd lip1 lip0 frsync 121 reserved reserved dls mdaisi aaisd ecc fecc1 fecc0 122 122 reserved -- -- -- -- -- -- -- -- 123 -- -- -- -- -- -- -- -- 124 124 r e3g7 51.rsr1 rab -- rnb lof rai ais oof 125 los reserved -- reserved reserved reserved reserved reserved 126 rua1 126 r e3g751.rsr2 -- -- -- -- reserved reserved reserved 127 fec -- -- -- -- -- -- -- -- 128 128 rl e3g751.rsrl1 acl ncl cofal lofl rail aisl oofl 129 losl reserved reserved reserved reserved reserved reserved reserved 12a rua1l 12a rl e3g751.rsrl2 -- -- -- -- reserved reserved reserved 12b fecl -- -- -- -- reserved reserved reserved 12c fel 12c e3g751.rsrie1 rw acie ncie cofaie lofie raiie aisie oofie losie 12 d reserved reserved reserved reserved reserved reserved reserved rua1ie 12e 12e rw e3g751.rsrie2 -- -- -- -- reserved reserved reserved fecie 12f -- -- -- -- reserved reserved reserved feie 130 - 132 130 reserved -- -- -- -- -- -- -- -- 133 -- -- -- -- -- -- -- -- 134 134 r e3g751.rfecr fe7 fe6 fe5 fe4 fe3 fe2 fe1 135 fe0 fe15 fe14 fe13 fe12 fe11 fe10 fe9 fe8
ds3170 ds3/e3 single - chip transceiver 125 of 230 address register type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 136- 13a 136 - reserved -- - - -- -- -- -- -- -- 13b -- -- -- -- -- -- -- -- 13c - 13e 13c - unused -- -- -- -- -- -- -- -- 13f -- -- -- -- -- -- -- -- 12.1.5 e3 g.832 register bit map table 12- 10 . e3 g.832 register bit map address reg ister type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 - bit 8 - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 118 118 rw e3g832.tcr -- -- tfebe afebed trdi ardid tfgd tais 119 reserved -- -- reserved reserved tgcc tnrc1 tnrc0 11a 11a rw e3g832.teir pbee cpeie pei feic1 feic0 fei tsei meims 11b -- -- -- -- reserved reserved cfbeie fbei 11c 11c rw e3g832.tmabr tpt2 tpt1 tpt0 ttigd tti3 tti2 tti1 tti0 11d -- -- -- -- -- -- -- -- 11e 11e rw e3g832.tngbr tnr7 tnr6 tnr5 tnr4 tnr3 tnr2 tnr1 tnr0 11f tgc7 tgc6 tgc5 tgc4 tgc3 tgc2 tgc1 tgc0 120 120 rw e3g832.rcr raile raild raiod raiad romd lip1 lip0 frsync 121 reserved pec dls mdaisi aaisd ecc fecc1 fecc0 122 122 rw e3g832.rmacr -- -- -- -- ept2 ept1 ept0 tied 123 -- -- -- -- -- -- -- -- 124 124 r e3g832.rsr1 reserved -- reserved lof rai ais oof 125 los -- reserved -- rptu rptm reserved reserved 126 rua1 126 r e3g832.rsr2 -- -- -- -- reserved fbec pec 127 fec -- -- -- -- -- -- -- -- 128 128 rl e3g832.rsrl1 gcl nrl cofal lofl rail aisl oofl 129 losl reserved -- til rptul rptml rptl reserved 12a rua1l 12a rl e3g832.rsrl2 -- -- -- -- reserved fbecl pecl 12b fecl -- -- -- -- reserved fbel pel 12c fel 12c rw e3g832.rsrie1 gcie nrie cofaie lofie raiie aisie oofie losie 12d reserved -- tiie rptuie rptmie rptie reserved rua1ie 12e 12e rw e3g832.rsrie2 -- -- -- -- reserved fbecie pecie fecie 12f -- - - -- -- reserved fbeie peie feie 130 130 r e3g832.rmabr -- rpt2 rpt1 rpt0 ti3 ti2 ti1 131 ti0 -- -- -- -- -- -- -- -- 132 132 r e3g832.rngbr rnr7 rnr6 rnr5 rnr4 rnr3 rnr2 rnr1 133 rnr0 rgc7 rgc6 rgc5 rgc4 rgc3 rgc2 rgc1 134 rgc0 134 r e3g832.rfecr fe7 fe6 fe5 fe4 fe3 fe2 fe1 135 fe0 fe15 fe14 fe13 fe12 fe11 fe10 fe9 136 fe8 136 r e3g832.rpecr pe7 pe6 pe5 pe4 pe3 pe2 pe1 137 pe0 pe15 pe14 pe13 pe12 pe11 pe10 pe9 138 pe8 138 r e3g832.rfber fbe 7 fbe 6 fbe 5 fbe 4 fbe 3 fbe 2 fbe 1 fbe 0 139 fbe fbe 15 fbe 14 fbe 13 fbe 12 fbe 11 fbe 9 10 fbe 8 13a 13a reserved -- -- -- -- -- -- -- -- 13b -- -- -- -- -- -- -- -- 13c - 13e 13c - unused -- -- -- -- -- -- -- -- 13f -- -- -- -- -- -- -- -- bits that are underlined are read - only; all other bit s are read - write.
ds3170 ds3/e3 single - chip transceiver 126 of 230 12.2 global registers table 12- 11 . global register map address register register description 000h global id register gl.idr 002h global control register 1 gl.cr1 004h global control register 2 gl.cr2 006h -- unused 008h -- unused 00ah global general purpose io control regist er gl.giocr 00ch -- unused 00eh -- unused 010h global interrupt status register gl.isr 012h global interrupt enable register gl.isrie 014h global status register gl.sr 016h global status register latched gl.srl 018h global status register interrupt enable gl.srie 01ah -- unused 01ch global general purpose io read register gl.giorr 01eh -- unused 12.2.1 register bit descriptions register name: gl.idr register description: global id register register address: 000h bit # 15 14 13 12 11 10 9 8 name id15 id14 id13 id12 id11 id10 id9 id8 bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 bits 15 to 12: device rev id bits 15 to 12 (id15 to id12). these bits of the device id register has same information as the four bits of jtag rev id portion of the jtag id register. jtag id[31:28]. bits 11 to 0: device code id bits 11 to 0 (id11 to id0). these bits of the device code id register has same information as the lower 12 bits of jtag code id portion of the jtag id register. jtag id[23:12].
ds3170 ds3/e3 single - chip transceiver 127 of 230 register name: g l.cr1 register description: global control register 1 register address: 002h bit # 15 14 13 12 11 10 9 8 name -- intm -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tmei meims gpm1 gpm0 pmu lsbcre rstdp rst default 0 0 0 0 0 0 1 0 bit 14: int pin mode (intm) this bit determines the inactive mode of the int pin. the int pin always drives low when active. 0 = pin is high impedance when not active 1 = pin drives high when not active bit 7: transmit manual error in sert (tmei) this bit is used insert an error if the port is configured for global error insertion. an error(s) is inserted at the next opportunity when this bit transitions from low to high. the gl.cr1 .meims bit must be clear for this bit to operate. bit 6: transmit manual error insert select (meims) this bit is used to select the source of the global manual error insertion signal 0 = global error insertion using tmei bit 1 = global error insertion using the gpio6 p in bits 5 and 4: global performance monitor update mode (gpm[1:0]) these bits select the global performance monitor register update mode. 00 = global pm update using the pmu bit 01 = global pm update using the gpio8 pin 1x = one second pm update using the internal one second counter bit 3: global performance monitor update register (pmu) this bit is used to update all of the performance monitor registers configured to use this bit. when this bit is toggled from low to high t he performance registers configu red to use this signal will be updated with the latest count value from the counters, and the counters will be reset. the bit should remain high until the performance register update status bit ( gl.sr .pms) goes high, th en it should be brought back low which clears the pms status bit. bit 2: latched status bit clear on read enable (lsbcre). this signal determines when latched status register bits are cleared. 0 = l atched status register bits are cleared on a write 1 = l a tched status register bits are cleared on a read bit 1: reset data path (rstdp). when this bit is set, it will force all of the internal data path registers to their default state. this bit must be set high for a minimum of 100ns. see the reset and power - down section 10.3 . note: the default state is a 1 (after a general reset, this bit will be set to one). 0 = normal operation 1 = force all data pa th registers to their default values bit 0: reset (rst). when this bit is set, all of the internal data path and status and control registers (except this rst bit), will be reset to their default state. this bit must be set high for a minimum of 100ns. see the reset and power - down section 10.3 . 0 = normal operation 1 = force all internal registers to their default values
ds3170 ds3/e3 single - chip transceiver 128 of 230 register name: gl.cr2 reg ister description: global control register 2 register address: 004h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- g8krs1 g8krs0 g8k0s g8kis default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- clad2 clad1 clad0 -- default 0 0 0 0 0 0 0 0 bits 11 to 10: global 8khz reference source [1:0] (g8krs[1:0]). these bits determine the source for the internally generated 8 khz reference as well as the internal one second reference, which is derived from the global 8 khz reference. the sou rce is selected from the clad clock or from the port 8kref clock source. see these bits are ignored when the g8kis bit = 1. table 10-12. global 8 khz reference source table table 10- 12 . global 8 khz reference source table g8kis gl.cr2 . g8krs[1:0] gl.cr2 . source 0 00 none, the 8khz divider is disabled. 0 01 derived from clad output clock 0 10 8kref source selected by p8krs[1:0] 0 11 undefined 1 xx g pio4 bit 9: gl obal 8khz reference output select (g8kos). this bit determines whether gpio2 pin is used for the global 8krefo output signal, or is used as specified by gl.giocr .gpio2s[1:0]. 0 = gpio2 pin mode selected by gl.giocr . 1 = gpio2 is the global 8krefo output signal selected by gpio2s[1:0] gl.cr2 .8krs[2:0] bit 8: global 8khz reference input select (g8kis). this bit determines whether gpio4 p in is used for the global 8krefi input signal, or is used as specified by gl.giocr .gpio4s[1:0]. g8krefi signal will be low if not selected. global 8kref pin signal will be low if not selected. 0 = gpio4 pin mode s elected by gl.giocr . 1 = gpio4 is the global 8krefi input signal for one second timer and port to use gpio4s[1:0] bits 3 to 1: clad io mode [2:0] (clad[2:0]). these bits control the clad. see table 10-11 . table 10- 11 . clad clock source settings clad[2:0] refclk (input) 000 44.736 mhz 001 34.368 mhz 010 51.84 mhz 011 19.44 mhz 100 77.76 mhz 101 undefined 11x undefined
ds3170 ds3/e3 single - chip transceiver 129 of 230 register name: gl.giocr register description: global general purpose io control register register a ddress: 00ah bit # 15 14 13 12 11 10 9 8 name gpio8s1 gpio8s0 gpio7s1 gpio7s0 gpio6s1 gpio6s0 gpio5s1 gpio5s0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name gpio4s1 gpio4s0 gpio3s1 gpio3s0 gpio2s1 gpio2s0 gpio1s1 gpio1s0 default 0 0 0 0 0 0 0 0 bits 15 to 14: general purpose io 8 select [1:0] (gpio8s[1:0]). these bits determine the function of the gpio8 pin. these selections are only valid if gl.cr1 .gpm[1:0] is not set to 01. 00 = input 01 = res erved 10 = output logic 0 11 = output logic 1 bits 13 to 12: general purpose io 7 select [1:0] (gpio7s[1:0]). these bits determine the function of the gpio7 pin. 00 = input 01 = reserved 10 = output logic 0 11 = output logic 1 bits 11 to 10 : general pur pose io 6 select [1:0] (gpio6s[1:0]). these bits determine the function of the gpio6 pin. these selections are only valid if gl.cr1 .meims=0. 00 = input 01 = reserved 10 = output logic 0 11 = output logic 1 bits 9 to 8 : general purpose io 5 select [1:0] (gpio5s[1:0]). these bits determine the function of the gpio5 pin. 00 = input 01 = reserved 10 = output logic 0 11 = output logic 1 bits 7 to 6: general purpose io 4 select [1:0] (gpio4s[1:0]). these bits determine the function of the gpio4 pin. these selections are only valid if gl.cr2 .g8kris=0. 00 = input 01 = reserved 10 = output logic 0 11 = output logic 1 bits 5 to 4: general purpose io 3 select [1:0] (gpio3s[1:0]). these b its determine the function of the gpio3 pin. 00 = input 01 = reserved 10 = output logic 0 11 = output logic 1 bits 3 to 2: general purpose io 2 select [1:0] (gpio2s[1:0]). these bits determine the function of the gpio2 pin. these selections are only valid if gl.cr2 . gkros=0. 00 = input 01 = port b status output selected by port.cr4 :gpiob[3:0] in port control registers 10 = output logic 0 11 = output logic 1
ds3170 ds3/e3 single - chip transceiver 130 of 230 bits 1 to 0: genera l purpose io 1 select [1:0] (gpio1s[1:0]). these bits determine the function of the gpio1 pin. 00 = input 01 = port a status output selected by port.cr4 :gpioa[3:0] in port control registers 10 = output logic 0 11 = output logic 1 register name: gl.isr register description: global interrupt status register register address: 010h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- pisr -- -- gsr bit 4: po rt interrupt status register (pisr) this bit is set when any of the bits in the port interrupt status registers ( port.isr ) are set. the int interrupt pin will be driven low when this bit is set and the gl.isrie .pisrie interrupt enable bit is enabled. bit 0: global status register interrupt status (gsr) this bit is set when any of the latched status register bits in the global latched status register ( gl.srl ) are set and enabled for interrupt. the int interrupt pin will be driven low when this bit is set and the gl.isrie .gsrie interrupt enable bit is enabled. register name: gl.isrie register description: global interrupt status registe r interrupt enable register address: 012h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- pisrie -- -- reserved gsrie default 0 0 0 0 0 0 0 0 bit 4: port interrupt sta tus register interrupt enable (pisrie) when this is enabled and the gl.isr . 0 = interrupt disabled pisr status bit is set, the int pin will be driven low. 1 = interrupt enabled bit 0: global status register interrupt status interrupt enable (gsrie) when this interrupt enable bit is enabled, and the gl.isr .gsr status bit is set, the int pin will be driven low. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 131 of 230 register name: gl.sr register description: global status regist er register address: 014h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- -- clol gpms bit 1 : clad loss of lock (clol) ? this bit is set when any of the plls in the clad are not locked t o the reference frequency. bit 0: global performance monitoring update status (gpms) this bit is set when all of the port performance register update status bits ( port.sr. pmu), that are enabled for global update control ( port.cr2. pmum=1), are set. it is an ?and? of all the globally enabled port pmu status bits. in global software update mode, the global update request bit ( gl.cr. gpmu) should be held high until this status bit goes high. 0 = the associated update request signal is low or not all register up dates are completed 1 = the requested performance register updates are all completed register name: gl.srl register description: global status register latched register address: 016h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- 8krefl cladl onesl cloll gpmsl bit 4: 8khz reference activity status latched (8krefl) this bit will be set when the 8 khz reference signal on the gpio4 pin is active. the gl.cr2 .g8kis bit must be set for the activity to be monitored. bit 3: clad reference clock activity status latched (cladl) this bit will be set when the clad pll reference clock signal on the refclk pin is active. bit 2: one second status latched (onesl) this b it will be set once a second. the gl.isr .gsr status bit will be set when this bit is set and the gl.srie .onesie bit is enabled. the int pin will be driven low if this bit is set and the gl.srie .onesie bit and the gl.isrie .gsrie bit are enabled. bit 1: clad loss of lock latched (cloll) this bit will be set when the gl.sr .clol status bit changes from low to high. the gl.isr .gsr bit will be set when this bit is set and the gl.srie .clolie bit is set and the int pin will be driven low if the gl.isrie .gsrie bit is also enabled. bit 0: global performance monitoring update status latched (gpmsl) this bi t will be set when the gl.sr .gpms status bit changes from low to high. this bit will set the gl.isr .gsr status bit if the gl.srie .gpmsie is enabled. this bit will drive the interrupt pin low if the gl.srie .gpmsie bit and the gl.isrie .gsrie bit are enabled.
ds3170 ds3/e3 single - chip transceiver 132 of 230 register name: gl.srie register description: global status register interrupt enable register address: 018h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- onesie clolie gpmsie default 0 0 0 0 0 0 0 0 bit 2: one second interrupt enable (onesie) this bit will drive the interrupt pin low if the gl.srl .onesl bit is set, and the gl.isrie .gsrie bit is enabled. 0 = interrupt disabled 1 = i nterrupt enabled bit 1: clad loss of lock interrupt enable (clolie) the interrupt pin will be driven when this bit is enabled, the gl.srl .cloll is set, and gl.isrie .gsrie bit is enabled. 0 = interrupt disabled 1 = interrupt enabled bit 0: global performanc e monitoring update status interrupt enable (gpmsie) the interrupt pin will be driven when this bit is enabled and the gl.srl .gpmsl bit is set and the gl.isrie .gsrie bit is e nabled. 0 = interrupt disabled 1 = interrupt enabled register name: gl.giorr register description: global general purpose io read register register address: 01ch bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 bits 7 to 0: general purpose io status [8:1]] (gpio[8:1] ) these bits reflect the input or output signal on the 8 general purpose io pins.
ds3170 ds3/e3 single - chip transceiver 133 of 230 12.3 p ort register 12.3.1 register bit descriptions table 12- 12 . port register map address register register description 0 40h port control register 1 port.cr1 0 42h port control regist er 2 port.cr2 0 44h port control register 3 port.cr3 0 46h port control register 4 port.cr4 0 48h unused -- 0 4ah port io invert c ontrol register 1 port.inv1 0 4ch port io invert control register 2 port.inv2 0 4eh unused -- 0 50h port interrupt status register port.isr 0 52h port status register port. sr 0 54h port status register latched port.srl 0 56h port status register interrupt enable port.srie 0 58h -- unused 0 5ah -- unused 0 5ch -- u nused 0 5eh -- unused
ds3170 ds3/e3 single - chip transceiver 134 of 230 register name: port.cr1 register description: port control register 1 register address: 040h bit # 15 14 13 12 11 10 9 8 name reserved pais2 pais1 pais0 lais1 lais0 bena reserved default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tmei meim -- pmum pmu pd rstdp rst default 0 0 -- 0 0 1 1 0 bits 14 to 12: payload ais select [2:0] (pais[2:0]). this bit controls when an unframed all ones signal is forced on the receive data path after the receive framer and payload loopback mux. default: payload ais always sent. pais[2:0] port.cr1 when ais is sent ais code 000 always ua1 001 when llb (no dlb) active ua1 010 when plb active ua1 011 when llb(no dlb) or plb active ua1 100 when los (no dlb) a ctive ua1 101 when oof active ua1 110 when oof, los. llb (no dlb), or plb active ua1 111 never none bits 11 to 10: line ais select [1:0] (lais[1 :0 ). these bits control when a ds3 framed ais or an unframed all ones signal is to be transmitted on tpos/tneg and/or txp/txn. the signal on tpos/tneg can be ami or unipolar. this signal is sent even when in diagnostic loopback and always over - rides signals from the framers. default: ais sent if dlb is enabled. lais[1:0] port.cr1 frame mode description ais code 00 ds3 automatic ais when dlb is enabled ( port.cr4 ds3ais .lbm = 1xx) 00 e3 automatic ais when dlb is enabled ua1 01 any send ua1 ua1 10 ds3 send ais ds3ais 10 e3 send ais ua1 11 any disabl e none bit 9: bert enable (bena). this bit is used to enable the transmit bert logic; the receive bert is always enabled. the bert pattern will replace the the system interface datastream (tser) into the payload datastream. 0 = tranmit bert logic disa bled and powered down
ds3170 ds3/e3 single - chip transceiver 135 of 230 1 = transmit bert logic enabled bit 7: transmit manual error insert (tmei) this bit is used to insert errors in all error insertion logic configured to use this bit when port.cr1 .meim=0. the error(s) will be inserted when this bit is toggled low to high. bit 6 : transmit manual error insert mode (meim). these bits select the method transmit manual error insertion for this port for error generators configured to use the external tmei signal. the global updates are controlled by the gl.cr1 .meims bit. 0 = port software update via port.cr1 .tmei 1 = global update source bit 4: performance monitor update mode (pmum). these bits select the method of updating the performance monitor registers. the gl obal updates are controlled by the gl.cr1 .gpmu bits. 0 = port software update 1 = global update bit 3: performance monitor register update (pmu) this bit is used to update all of the performance monitor registers configured to use this bit when port.cr1 . pmum=0. the performance registers configured to use this signal will be updated with the latest count value and the counters reset when this bit is toggled low to high. the bit should remain high until the performance register update status bit ( port.sr .pm s) goes high, then it should be brought back low which clears the pms status bit. bit 2: power - down (pd). when this bit is set, the liu and digital logic for this port are powered down and considered ?out of service?. the logic is powered down by stoppin g the clocks. see the reset and power - down section 10.3 . 0 = normal operation 1 = power - down port circuits (default state) bit 1: reset data path (rstdp). when this bit is set, it will force all of the internal data path registers to their default state. this bit must be set high for a minimum of 100ns and then set back low. see the reset and power - down section 10.3 . note: the default state of this bit is 1 (after a general reset (port or global), this bit will be set to one). 0 = normal operation 1 = force all data path registers to their de fault values bit 0: reset (rst). when this bit is set, it will force all the internal data path and status and control registers (except this rst bit) of this port to their default state. see the reset and power -do wn section 10.3 . this bit must be set high for a minimum of 100ns and then set back low. this software bit is logically or?ed with the inverted hardware signal rst and the gl.cr1 .rst bit. 0 = normal operation 1 = force all internal registers to their default values register name: port.cr2 register description: port control register 2 register address: 042h bit # 15 14 13 12 11 10 9 8 name tlen t ts rmon tlbo reserved lm2 lm1 lm0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name reserved reserved fm2 fm1 fm0 reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15: transmit line io signal enable (tlen). this bit is used to enabl e to transmit line interface output pins tlclk, tpos/tdat and tneg. 0 = disable, force outputs low 1 = enable normal operation bit 14: transmit liu tri - state (tts) this bit is used to tri - state the transmit txp and txn pins. the liu is still powered up w hen the pins are tri - stated. it has no effect when the liu is disabled and powered down.
ds3170 ds3/e3 single - chip transceiver 136 of 230 0 = txp and txn driven 1 = txp and txn tri - stated bit 13: receive liu monitor mode (rmon) this bit is used to enable the receive liu monitor mode pre - amplifier. ena bling the pre - amplifier adds about 20 db of linear amplification for use in monitor applications where the signal has been reduced 20 db using resistive attenuator circuits. 0 = disable the 20 db pre - amp 1 = enable the 20 db pre - amp bit 12: transmit liu lb o (tlbo) this bit is used enable the transmit lbo circuit which causes the transmit signal to have a wave shape that approximates about 225 feet of cable. this is used to reduce near end crosstalk when the cable lengths are short. this signal is only valid in ds3 liu mode. 0 = txp and txn have full amplitude signals 1 = txp and txn signals approximate 225 feet of cable bits 10 to 8 : port interface mode (lm[2:0]). the lm[2:0] bits select main port interface operational modes. the default state disables the liu and the ja. table 10- 26 . line mode select bits lm[2:0] line.tcr . tzsd & line.rcr lm[2:0] ( .rzsd port.cr2 line code ) liu ja 0 000 b3zs/hdb3 off off 0 001 b3zs/hdb3 on off 0 010 b3zs/hdb3 on tx 0 011 b3zs/hdb3 on rx 1 000 ami off off 1 001 ami on off 1 010 ami on tx 1 011 ami on rx x 1xx uni off off bits 5 to 3: framing mode (fm[2:0]). the fm[2:0] bits select main framing operational modes. default: ds3 c - bit. fm[2:0] description line code figure 0 00 ds3 c - bit framed b3zs/ami/uni figure 7 - 1 0 01 ds3 m23 framed b3zs/ami/uni figure 7 - 1 0 10 e3 g.751 famed hdb3/ami/uni figure 7 - 1 0 11 e3 g.832 framed hdb3/ami/uni figure 7 - 1 1 00 ds3 unframed b3zs/ami/ uni figure 7 - 2 1 01 undefined --- 1 10 e3 unframed hdb3/ami/uni figure 7 - 2 1 11 undefined ---
ds3170 ds3/e3 single - chip transceiver 137 of 230 register name: port.cr3 register description: port c ontrol register 3 register address: 044h bit # 15 14 13 12 11 10 9 8 name -- -- rclks rsofos reserved tclks tsofos reserved default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name p8krs1 p8krs0 p8kref loopt cladc rfts tfts tlts default 0 0 0 0 0 0 0 0 bit 13: receive clock output select (rclks). this bit is used to select the function of the rgclk / rclko pins. see table 10-24 . 0 = selects the rgclk signal, or the drive low pin function. 1 = selects rclko signal. bit 12: receive start of frame output select (rsofos). this bit is to select the function of the rsofo / rden pins. see table 10-23 . 0 = selects rden signal. 1 = selects rso fo signal. bit 10: transmit clock output select (tclks). this bit is used to select the function of the tgclk / tclko pins. see table 10-22 . 0 = selects tgclk signal. 1 = selects tclko signal. bit 9: transmit start of frame output select (tsofos). this bit is used to select the function of the tsofo / tden pins. see table 10-21 . 0 = selects tden signal. 1 = selects tsofo signal. bits 7 to 6: por t 8 khz reference source select (p8krs[1:0]). this bit selects the source of the 8 khz reference from the port sources. the 8k reference for this port can be used as the global 8k reference source. see table 10-13 . table 10- 13. port 8 khz reference source table source port.cr3 . p8krs[1:0] 0x undefined 10 internal receive framer clock 11 internal transmit framer clock bit 5: port 8 khz reference source (p8kref). this bit selects the source of the 8 khz reference for one second timer. 0 = 8 khz reference from glo bal source 1 = 8 khz reference from port?s selected source bit 4: loop time enable (loopt). when this bit is set, the port is in loop time mode. the transmit clock is set to the receive clock from the rlclk pin or the recovered clock from the liu or the clad clock and the tclki pin is not used. this function of this bit is conditional on other control bits. see table 10-4 for more details. 0 = normal transmit clock operation 1 = transmit using the recei ve clock bit 3: clad transmit clock source control (cladc). this bit is used to enable the clad clocks as the source of the internal transmit clock. this function of this bit is conditional on other control bits. see table 10-4 0 = use clad clocks for the transmit clock as appropriate for more details. 1 = do not use clad clocks for the transmit clock ? (if no loopback is enabled, tclki is the source)
ds3170 ds3/e3 single - chip transceiver 138 of 230 bit 2: receive framer io signal timing select (rfts). this bit controls the timing reference for the signals on the receive framer interface io pins. the pins controlled are rser, rsofo / rden. see table 10-8 for more details. 0 = use output clocks for timi ng reference 1 = use input clocks for timing reference bit 1: transmit framer io signal timing select (tfts). this bit controls the timing reference for the signals on the transmit framer interface io pins. the pins controlled are tsofin, tser, and tsofo / tden. see table 10-7 for more details. 0 = use output clocks for timing reference 1 = use input clocks for timing reference bit 0: transmit line io signal timing select (tlts). this bit controls the t iming reference for the signals on the transmit line interface io pins. the pins controlled are tpos / tdat and tneg. see table 10-6 for more details. 0 = use output clocks for timing reference 1 = use inp ut clocks for timing reference register name: port.cr4 register description: port control register 4 register address: 046h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- reserved lbm2 lbm1 lbm0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name gpiob3 gpiob2 gpiob1 gpiob0 gpioa3 gpioa2 gpioa1 gpioa0 default 0 0 0 0 0 0 0 0 bits 10 to 8: loopback mode [2:0] (lbm[2:0]). these bits select the loopback modes for analog loopback (alb), line loopback (llb), payload loopback (plb) and diagno stic loopback (dlb). see table 10-17 for the loopback select codes. default: no loopback. lbm[2:0] alb llb plb dlb 000 0 0 0 0 001 1 0 0 0 010 0 1 0 0 011 0 0 1 0 10x 0 0 0 1 1 10 0 1 0 1 111 0 0 0 1 bits 7 to 4: general purpose io b output select[3:0] (gpiob[3:0]) these bits determine which alarm status sig nal to output on the gpio2, pin. the gpio pin must be enabled by setting the bits in the gl.giocr and gl.cr2 registers to output the selected alarm signal. see table 10-15. see table 10-16 for the alarm select codes. bits 3 to 0: general purpose io a output select[3:0] (gpioa[3:0]) these bits determine which alarm status s ignal to output on the gpio1 pin. the gpio pin must be enabled for output by setting the bits in the gl.giocr register . see table 10-15 for configuration settings . see table 10-16 below for the alarm select codes.
ds3170 ds3/e3 single - chip transceiver 139 of 230 table 10- 16 . gpio port alarm monitor select gpio(a/b)[3:0] port.cr4 line los ds3/e3 oof ds3/e3 lof ds3/e3 ais ds3/e3 rai ds3 idle 0000 x 0001 x 0010 x 0011 x 0100 x 0101 x 0110 0111 1000 1001 1010 1011 x x x 1100 1101 x x x 1110 x x 1111 x x x x x x
ds3170 ds3/e3 single - chip transceiver 140 of 230 register name: port.inv1 register description: port io invert control register 1 register address: 04ah bit # 15 14 13 12 11 10 9 8 name reserved reserved -- tsofoi reserved tseri tohsi tohei default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tohi tohcki tsofii tnegi tdati tlcki tckoi tckii default 0 0 0 0 0 0 0 0 bit 12 : tsofo / tden/ invert (tsofoi). this bit inverts the tsofo / tden pin when set. bit 10 : tser invert (tseri). this bit inverts the tser pin when set. bit 9 : tohsof invert (tohsi). this bit inverts the tohsof pin when set. bit 8 : tohen invert (tohei). this bit inverts the tohen pin when set. bit 7 : toh invert (tohi). this bit inverts the toh pin when set. bit 6 : tohclk invert (tohcki). this bit inverts the tohclk pin when set. bit 5 : tsofin invert (tsofii). this bit inverts the tsofin pin when set. bit 4 : tneg invert (tnegi). this bit inverts the tneg pin when set. bit 3 : tdat invert (t dati). this bit inverts the tdat pin when set. bit 2 : tlclk invert (tlcki). this bit inverts the tlclk pin when set. bit 1 : tclko / tgclk invert (tckoi). this bit inverts the tclko / tgclk pin when set. bit 0 : tclki invert (tckii). this bit inverts the tclki pin when set. register name: port.inv2 register description: port io invert control register 2 register address: 04ch bit # 15 14 13 12 11 10 9 8 name -- reserved reserved rsofoi -- rseri rohsi -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rohi rohcki -- rnegi rposi rlcki rclkoi -- default 0 0 0 0 0 0 0 0 bit 12 : rsofo / rden invert (rsofoi). this bit inverts the rsofo / rden pin when set. bit 10 : rser invert (rseri). this bit inverts the rser pin when set. bit 9 : rohsof invert (rohsi). this bit inverts the rohsof pin when set. bit 7 : roh invert (rohi). this bit inverts the roh pin when set. bit 6 : rohclk invert (rohcki). this bit inverts the rohclk pin when set. bit 4 : rneg / rlcv invert (rnegi). this bit inverts the rneg / rlcv when set. bit 3 : rpos / rdat invert (rposi). this bit inverts the rpos / rdat pin when set. bit 2 : rlclk invert (rlcki). this bit inverts the rlclk pin when set. bit 1 : rclko / rgclk invert (rclkoi). this bit inverts the rclk o / rgclk pin when set.
ds3170 ds3/e3 single - chip transceiver 141 of 230 register name: port.isr register description: port interrupt status register register address: 050h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- psr lcsr bit # 7 6 5 4 3 2 1 0 name ttsr fsr hsr reserved bsr reserved reserved fmsr bit 9: port status register interrupt status (psr) this bit is set when any of the latched status register bits, that are enabled for interrupt, in the port.srl register are set. the interrupt pin will be driven when this bit is s et and the gl.isrie .pisrie bit is set. bit 8: line code status register interrupt status (lcsr) this bit is set when any of the latched status register bits, that are enabled for interrupt, in the b3zs/hdb3 line encoder/decoder block are set. the interrupt pin will be driven when this bit is set and the gl.isrie .pisrie bit is set. bit 7: trail trace status register interrupt status (ttsr) this bit is set when any of the l atched status register bits, that are enabled for interrupt, in the trail trace block are set. the interrupt pin will be driven when this bit is set and the gl.isrie .pisrie bit is set. bit 6: feac status register interrupt status (fsr) this bit is set when any of the latched status register bits, that are enabled for interrupt, in the feac block are set. the interrupt pin will be driven when this bit is set and the gl.isrie .pisrie bit is set. bit 5: hdlc status register interrupt status (hsr) this bit is set when any of the latched status register bits, that are enabled for interrupt, in the hdlc block are set. the interrupt pin will be driven when this bit is set and the gl.isrie .pisrie bit is set. bit 4: bert status register interrupt status (bsr) this bit is set when any of the latched status register bits, that are enabled for interrupt, in the bert block are set. the interrupt pin will be driven when this bit is set and the gl.isrie .pisrie bit is set. bit 0: framer status register interrupt status (fmsr) this bit is set when any of the latched status register bits, that are enabled for interrupt, in the active ds3 or e3 framer block are set. the interrupt pin will be driven when this bit is set and the gl.isrie .pisrie bit is set. register name: port.sr register description: port status regist er register address: 052h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- tdm rlol pms bit 2: transmit driver monitor status (tdm) this bits indicates the status of the transmit monitor circuit in the transmit liu. 0 = transmit output not over loaded 1 = transmit signal is overloaded
ds3170 ds3/e3 single - chip transceiver 142 of 230 bit 1: receive loss of lock status (rlol) this bits indicates the status of the receive liu clock recovery pll circuit. 0 = locked to the incoming signal 1 = not locked to the incoming signal bit 0: performance monitoring update status (pms) this bits indicates the status of all active performance monitoring register and counter update signals in this port. it is an ?and? of all update status bits and is not s et until all performance registers are updated and the counters reset. in software update modes, the update request bit port.cr1.pmu should be held high until this status bit goes high. 0 = the associated update request signal is low 1 = the requested perf ormance register updates are all completed register name: port.srl register description: port status register latched register address: 054h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name rlclkl tclki l -- -- -- tdml rloll pmsl bit 7: receive line clock activity status latched (rlclkl) this bit will be set when the signal on the rlclk pin or the recovered clock from the liu for this port is active. bit 6: transmit input clock activity status latched (t clkil) this bit will be set when the signal on the tclki pin for this port is active. bit 2: transmit driver monitor status latched (tdml) this bit will be set when the port.sr. tdm status bit changes from low to high. this bit will also set the port.isr. ps r status bit if the port.srie. tdmie bit is enabled. the interrupt pin will be driven when this bit is set, the port.srie. tdmie bit is set, and the corresponding gl.isrie. pisrie bit is also set. bit 1: receive loss of lock status latched (rloll) this bit will be set when the port.sr .rlol status bit changes from low to high. this bit will also set the port.isr .psr status bit if the port.srie .rlolie bit is enabled. the interrupt pin will be driven when this bit is set, the port.srie .rlolie bit is set, an d the corresponding gl.isrie .pisrie bit is also set. bit 0: performance monitoring update status latched (pmsl) this bit will be set when the port.sr .pms status bit changes from low to high. this bit will also set the port.isr .psr status bit if the port.sr ie .pmuie bit is enabled. the interrupt pin will be driven when this bit is set, the port.srie .pmuie bit is set, and the port.srie .pmsie bit are set. register name: port.srie register description: port status register interrupt enable register address : 056h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- tdmie rlolie pmsie default 0 0 0 0 0 0 0 0 bit 2: transmit driver monitor latched status interrupt enable (t dmie) the interrupt pin will be driven when this bit is enabled and the port.srl .tdml bit is set and the gl.isrie .pisrie bit is enabled.
ds3170 ds3/e3 single - chip transceiver 143 of 230 bit 1: receive loss of lock latched status interrupt enable (rlolie) the int errupt pin will be driven when this bit is enabled and the port.srl .rloll bit is set and the bit in gl.isrie .pisrie bit is enabled. bit 0: performance monitoring update latched status interrupt enable (pmsie) the interrupt pin will be driven when this bit is enabled and the port.srl .pmsl bit is set and the bit in gl.isrie .pisrie bit is enabled.
ds3170 ds3/e3 single - chip transceiver 144 of 230 12.4 bert 12.4.1 bert register map the bert utilizes twelve registers. table 12- 13 . bert register map address register register description 060h bert.cr bert control register 062h bert.pcr bert pattern configuration register 064h bert.spr1 bert seed/pattern register #1 066h bert.spr2 bert s eed/pattern register #2 068h bert.teicr bert transmit error insertion control register 06ah -- unused 06ch bert.sr bert status register 06eh bert.srl bert status register latched 070h bert.srie bert status register interrupt enable 072h -- unused 07 4h bert.rbecr1 bert receive bit error count register #1 076h bert.rbecr2 bert receive bit error count register #2 078h bert.rbcr1 bert receive bit count register #1 07ah bert.rbcr2 bert receive bit count register #2 07ch -- unused 07eh -- unused 12.4.2 ber t register bit descriptions register name: bert.cr register description: bert control register register address: 060h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pmum lpmu rnpl rpic mpr aprd tnpl tpic default 0 0 0 0 0 0 0 0 bit 7: performance monitoring update mode (pmum) ? when 0, a performance monitoring update is initiated by the lpmu register bit. when 1, a performance monitoring update is initiated by the global or port pmu r egister bit. note: if the lpmu bit or the global or port pmu bit is one, changing the state of this bit may cause a performance monitoring update to occur. bit 6: local performance monitoring update (lpmu) ? this bit causes a performance monitoring update to be initiated if local performance monitoring update is enabled (pmum = 0) . a 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1) . for a second performance monitoring update to be initiated, this bit must be set to 0, and back to 1 . if lpmu goes low before the pms bit goes high; an update might not be performed . this bit has no affect when pmum=1. bit 5: receive new pattern load (rnpl) ? a zero to one transition of this bit will cause the programmed test pattern (qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0]) to be loaded in to the receive pattern generator. this bit
ds3170 ds3/e3 single - chip transceiver 145 of 230 must be changed to zero and back to one for another pattern to be loaded. loading a new pattern will forces the rec eive pattern generator out of the ?sync? state which causes a resynchronization to be initiated. note: qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0] must not change from the time this bit transitions from 0 to 1 until four receive clock cycles after this bi t transitions from 0 to 1. bit 4: receive pattern inversion control (rpic) ? when 0, the receive incoming data stream is not altered. when 1, the receive incoming data stream is inverted . bit 3: manual pattern resynchronization (mpr) ? a zero to one transi tion of this bit will cause the receive pattern generator to resynchronize to the incoming pattern. this bit must be changed to zero and back to one for another resynchronization to be initiated. note: a manual resynchronization forces the receive pattern generator out of the ?sync? state. bit 2: automatic pattern resynchronization disable (aprd) ? when 0, the receive pattern generator will automatically resynchronize to the incoming pattern if six or more times during the current 64 - bit window the incoming data stream bit and the receive pattern generator output bit did not match. when 1, the receive pattern generator will not automatically resynchronize to the incoming pattern . bit 1: transmit new pattern load (tnpl) ? a zero to one transition of this bit will cause the programmed test pattern (qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0]) to be loaded in to the transmit pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. note: qrss, pts, plf[4:0}, ptf[4:0] , and bsp[31:0] must not change from the time this bit transitions from 0 to 1 until four transmit clock cycles after this bit transitions from 0 to 1. bit 0: transmit pattern inversion control (tpic) ? when 0, the transmit outgoing data stream is not alte red. when 1, the transmit outgoing data stream is inverted . register name: bert.pcr register description: bert pattern configuration register register address: 062h bit # 15 14 13 12 11 10 9 8 name -- -- -- ptf4 ptf3 ptf2 ptf1 ptf0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- qrss pts plf4 plf3 plf2 plf1 plf0 default 0 0 0 0 0 0 0 0 bits 12 to 8: pattern tap feedback (ptf[4:0]) ? these five bits control the prbs ?tap? feedback of the pattern generator. the ?tap? feedback will be from bit y of the pattern generator (y = ptf[4:0] +1). these bits are ignored when programmed for a repetitive pattern. for a prbs signal, the feedback is an xor of bit n and bit y. bit 6: qrss enable (qrss) ? when 0, the pattern generator configuration is cont rolled by pts, plf[4:0], and ptf[4:0], and bsp[31:0]. when 1, the pattern generator configuration is forced to a prbs pattern with a generating polynomial of x 20 + x 17 + 1. the output of the pattern generator will be forced to one if the next fourteen outp ut bits are all zero. bit 5: pattern type select (pts) ? when 0, the pattern is a prbs pattern. when 1, the pattern is a repetitive pattern . bits 4 to 0: pattern length feedback (plf[4:0]) ? these five bits control the ?length? feedback of the pattern gene rator. the ?length? feedback will be from bit n of the pattern generator (n = plf[4:0] +1). for a prbs signal, the feedback is an xor of bit n and bit y. for a repetitive pattern the feedback is bit n.
ds3170 ds3/e3 single - chip transceiver 146 of 230 register name: bert.spr1 register description: bert seed/pattern register #1 register address: 064h bit # 15 14 13 12 11 10 9 8 name bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 default 0 0 0 0 0 0 0 0 bi ts 15 to 0: bert seed/pattern (bsp[15:0]) ? lower sixteen bits of 32 bits. register description follows next register. register name: bert.spr2 register description: bert seed/pattern register #2 register address: 066h bit # 15 14 13 12 11 10 9 8 na me bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 default 0 0 0 0 0 0 0 0 bits 15 to 0: bert seed/pattern (bsp[31:16]) - upper 16 bits of 32 bits. be rt seed/pattern (bsp[31:0]) ? these 32 bits are the programmable seed for a transmit prbs pattern, or the programmable pattern for a transmit or receive repetitive pattern. bsp(31) will be the first bit output on the transmit side for a 32 - bit repetitive p attern or 32- bit length prbs. bsp(31) will be the first bit input on the receive side for a 32- bit repetitive pattern. register name: bert.teicr register description: bert transmit error insertion control register register address: 068h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- teir2 teir1 teir0 bei tsei meims default 0 0 0 0 0 0 0 0 bits 5 to 3: transmit error insertion rate (teir[2:0]) ? these three bits indicate the rate at which errors are inserted in the output data stream . one out of every 10 n bits is inverted. teir[2:0] is the value n. a teir[2:0] value of 0 disables error insertion at a specific rate. a teir[2:0] value of 1 result in every 10 th bit being inverted. a teir[2:0] value of 2 result in every 100 th bit being inverted. error insertion starts when this register is written to with a teir[2:0] value that is nonzero. if this register is written to during the middle of an error insertion process, the new error rat e will be started after the next error is inserted.
ds3170 ds3/e3 single - chip transceiver 147 of 230 teir[2:0] error rate 000 disabled 001 1*10 -1 010 1*10 -2 011 1*10 -3 100 1*10 -4 101 1*10 -5 110 1*10 -6 111 1*10 -7 bit 2: bit error insertion enable (bei) ? when 0, single bit error insertion is di sabled. when 1, single bit error insertion is enabled. bit 1: transmit single error insert (tsei) ? this bit causes a bit error to be inserted in the transmit data stream if manual error insertion is disabled (meims = 0) and single bit error insertion is e nabled . a 0 to 1 transition causes a single bit error to be inserted. for a second bit error to be inserted, this bit must be set to 0, and back to 1. note: if meims is low, and this bit transitions more than once between error insertion opportunities, onl y one error will be inserted. bit 0: manual error insert mode select (meims) ? when 0, error insertion is initiated by the tsei register bit. when 1, error insertion is initiated by the transmit manual error insertion signal (tmei). note: if tmei or tsei i s one, changing the state of this bit may cause a bit error to be inserted. register name: bert.sr register description: bert status register register address: 06ch bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 na me -- -- -- -- -- pms bec oos bit 3: performance monitoring update status (pms) ? t his bit indicates the status of the receive performance monitoring register (counters) update. this bit will transition from low to high when the update is completed. pms will be forced low when the lpmu bit (pmum = 0) or the global or port pmu bit (pmum=1) goes low . bit 1: bit error count (bec) ? when 0, the bit error count is zero . when 1, the bit error count is one or more. this bit is cleared when the user updates the bert counters via the pmu bit (bert.cr). bit 0: out of synchronization (oos) ? when 0, the receive pattern generator is synchronized to the incoming pattern. when 1, the receive pattern generator is not synchronized to the incoming pattern.
ds3170 ds3/e3 single - chip transceiver 148 of 230 register name : bert.srl register description: bert status register latched register address: 06eh bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- pmsl bel becl oosl bit 3: performance monitoring update status la tched (pmsl) ? this bit is set when the pms bit transitions from 0 to 1. bit 2: bit error latched (bel) ? this bit is set when a bit error is detected . bit 1: bit error count latched (becl) ? this bit is set when the bec bit transitions from 0 to 1. bit 0: out of synchronization latched (oosl) ? this bit is set when the oos bit changes state. register name: bert.srie register description: bert status register interrupt enable register address: 070h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- - - -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- pmsie beie becie oosie default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status interrupt enable (pmsie) ? this bit enables an interrupt if the pmsl bit is set. 0 = inte rrupt disabled 1 = interrupt enabled bit 2: bit error interrupt enable (beie) ? this bit enables an interrupt if the bel bit is set and the gl.isrie .psrie bit is set. 0 = interrupt disabled 1 = interrupt enable d bit 1: bit error count interrupt enable (becie) ? this bit enables an interrupt if the becl bit is set and the gl.isrie .psrie bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: out of synchronizat ion interrupt enable (oosie) ? this bit enables an interrupt if the oosl bit is set and the gl.isrie .psrie bit is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 149 of 230 register name: bert.rbecr1 register descript ion: bert receive bit error count register #1 register address: 074h bit # 15 14 13 12 11 10 9 8 name bec15 bec14 bec13 bec12 bec11 bec10 bec9 default bec8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bec7 bec6 bec5 bec4 bec3 bec2 bec1 default bec0 0 0 0 0 0 0 0 0 bits 15 to 0: bit error count (bec[15:0]) ? lower sixteen bits of 24 bits. register description follows next register. register name: bert.rbecr2 register description: bert receive bit error count register #2 register address: 076h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bec23 bec22 bec21 bec20 bec19 bec18 bec17 default bec16 0 0 0 0 0 0 0 0 bits 7 to 0: bit error count (bec[23:16]) - upper 8 - bits of register . bit error count (bec[23:0]) ? these twenty - four bits indicate the number of bit errors detected in the incoming data stream. this count stops incrementing when it reaches a count of ff ffffh . this bit error counter will not increment when an oos conditio n exists . this register is updated via the pmu signal (see section 10.4.5 )
ds3170 ds3/e3 single - chip transceiver 150 of 230 register name: bert.rbcr1 register description: receive bit count register #1 register address: 078h bit # 15 14 13 12 11 10 9 8 name bc15 bc14 bc13 bc12 bc11 bc10 bc9 default bc8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bc7 bc6 bc5 bc4 bc3 bc2 bc1 default bc0 0 0 0 0 0 0 0 0 bits 15 to 0: bit count (bc[15:0]) ? lower sixteen bits of 32 bits. register description follows next register. register name: bert.rbcr2 register description: receive bit count register #2 register address: 07ah bit # 15 14 13 12 11 10 9 8 name bc31 bc30 bc29 bc28 bc27 bc26 bc25 default bc24 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bc23 b c22 bc21 bc20 bc19 bc18 bc17 default bc16 0 0 0 0 0 0 0 0 bits 15 to 0: bit count (bc[31:16]) - upper 16 bits of 32 bits. bit count (bc[31:0]) ? these thirty - two bits indicate the number of bits in the incoming data stream. this count stops incrementing when it reaches a count of ffff ffffh . this bit counter will not increment when an oos condition exists . this register is updated via the pmu signal (see section 10.4.5 )
ds3170 ds3/e3 single - chip transceiver 151 of 230 12.5 b3zs/hdb3 line encoder/decoder 12.5.1 transmit side line encoder/decoder register map the transmit side utilizes one register. table 12- 14 . transmit side b3zs/hdb3 line encoder/decoder register map address register register description 08ch line.tcr l ine transmit control register 08eh -- unused 12.5.1.1 register bit descriptions register name: line.tcr register description: line transmit control register register address: 08ch bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- tzsd exzi bpvi tsei meims default 0 0 0 0 0 0 0 0 bit 4: transmit zero suppression encoding disable (tzsd) ? when 0, the b3zs/hdb3 encoder performs zero suppression (b3zs or hdb3) and ami encoding. when 1, zero suppression (b3zs or hdb3) encoding is disabled, and only ami encoding is performed. bit 3: excessive zero insert enable (exzi) ? when 0, excessive zero (exz) event insertion is disabled. when 1, exz event insertion is enabled. bit 2: bipolar violation in sert enable (bpvi) ? when 0, bipolar violation (bpv) insertion is disabled. when 1, bpv insertion is enabled. bit 1: transmit single error insert (tsei) ? this bit causes an error of the enabled type(s) to be inserted in the transmit data stream if manual error insertion is disabled (meims = 0) . a 0 to 1 transition causes a single error to be inserted. for a second error to be inserted, this bit must be set to 0, and back to 1. note: if meims is low, and this bit transitions more than once between error in sertion opportunities, only one error will be inserted. bit 0: manual error insert mode select (meims) ? when 0, error insertion is initiated by the tsei register bit. when 1, error insertion is initiated by the transmit manual error insertion signal (tmei ). note: if tmei or tsei is one, changing the state of this bit may cause an error to be inserted.
ds3170 ds3/e3 single - chip transceiver 152 of 230 12.5.2 receive side line encoder/decoder register map the receive side utilizes six registers. table 12- 15 . receive side b3zs/hdb3 line encoder/decoder register map address register register description 090h line.rcr line receive control register 092h -- unused 094h line.rsr line receive status register 096h line.rsrl line receive status register latched 098h li ne.rsrie line receive status register interrupt enable 09ah -- unused 09ch line.rbpvcr line receive bipolar violation count register 09eh line.rexzcr line receive excessive zero count register 12.5.2.1 register bit descriptions register name: line.rcr regist er description: line receive control register register address: (0.2.4.6)90h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- e3cve rezsf rdzsf rzsd default 0 0 0 0 0 0 0 0 b it 2: e3 code violation enable (e3cve) ? when 0, the bipolar violation count will be a count of bipolar violations. when 1, the bipolar violation count will be a count of e3 line coding violations . note: e3 line coding violations are defined as consecutive bipolar violations of the same polarity in itu o.161. this bit is ignored in b3zs mode. bit 2: receive bpv error detection zero suppression code format (rezsf) ? when 0, bpv error detection detects a b3zs signature if a zero is followed by a bipolar viola tion (bpv), and an hdb3 signature if two zeros are followed by a bpv . when 1, bpv error detection detects a b3zs signature if a zero is followed by a bpv that has the opposite polarity of the bpv in the previous b3zs signature, and an hdb3 signature if two zeros are followed by a bpv that has the opposite polarity of the bpv in the previous hdb3 signature. note: immediately after a reset, this bit is ignored. the first b3zs signature is defined as a zero followed by a bpv, and the first hdb3 signature is de fined as two zeros followed by a bpv. all subsequent b3zs/hdb3 signatures will be determined by the setting of this bit. note: the default setting (rezsf = 0) conforms to itu o.162. the default setting may falsely decode actual bpvs that are not codewords . it is recommended that rezsf be set to one for most applications. this setting is more robust to accurately detect codewords. bit 1: receive zero suppression decoding zero suppression code format (rdzsf) ? when 0, zero suppression decoding detects a b3zs signature if a zero is followed by a bipolar violation (bpv), and an hdb3 signature if two zeros are followed by a bpv. when 1, zero suppression decoding detects a b3zs signature if a zero is followed by a bpv that has the opposite polarity of the bpv in the previous b3zs signature, and an hdb3 signature if two zeros are followed by a bpv that has the opposite polarity of the bpv in the previous hdb3 signature. note: immediately after a reset ( drst or rst low), this bit is ignored. the first b3zs signa ture is defined as a zero followed by a bpv, and the first hdb3 signature is defined as two zeros followed by a bpv. all subsequent b3zs/hdb3 signatures will be determined by the setting of this bit.
ds3170 ds3/e3 single - chip transceiver 153 of 230 bit 0: receive zero suppression decoding disable (rzsd) ? when 0, the b3zs/hdb3 decoder performs zero suppression (b3zs or hdb3) and ami decoding. when 1, zero suppression (b3zs or hdb3) decoding is disabled, and only ami decoding is performed. register name: line.rsr register description: line receive statu s register register address: (0.2.4.6)94h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- exzc bpvc los bit 3: excessive zero count (exzc) ? when 0, the excessive zero count is zero . when 1, the e xcessive zero count is one or more. bit 1: bipolar violation count (bpvc) ? when 0, the bipolar violation count is zero . when 1, the bipolar violation count is one or more. bit 0: loss of signal (los) ? when 0, the receive line is not in a loss of signal ( los) condition. when 1, the receive line is in an los condition. see section 10.10.4 register name: line.rsrl register description: line receive status register latched register address: (0.2.4.6)96h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- zscdl exzl exzcl bpvl bpvcl losl bit 5: zero suppression code detect latched (zscdl) ? this bit is set when a b3zs or hdb3 signature is detected. bit 4: excessive ze ro latched (exzl) ? this bit is set when an excessive zero event is detected on the incoming bipolar data stream . bit 3: excessive zero count latched (exzcl) ? this bit is set when the line.rsr.exzc bit transitions from zero to one. bit 2: bipolar violatio n latched (bpvl) ? this bit is set when a bipolar violation (or e3 lcv if enabled) is detected on the incoming bipolar data stream . bit 1: bipolar violation count latched (bpvcl) ? this bit is set when the line.rsr.bpvc bit transitions from zero to one. bi t 0: loss of signal change latched (losl) ? this bit is set when the line.rsr.los bit changes state. note: when zero suppression (b3zs or hdb3) decoding is disabled, the los condition is cleared, and cannot be detected.
ds3170 ds3/e3 single - chip transceiver 154 of 230 register name: line.rsrie registe r description: line receive status register interrupt enable register address: (0.2.4.6)98h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- zscdie exzie exzcie bpvie bpvcie losie de fault 0 0 0 0 0 0 0 0 bit 5: zero suppression code detect interrupt enable (zscdie) ? this bit enables an interrupt if the line.rsrl .zscdl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this p ort is set. 0 = interrupt disabled 1 = interrupt enabled bit 4: excessive zero interrupt enable (exzie) ? this bit enables an interrupt if the line.rsrl .exzl bit is set and the bit in gl.isrie .psrie[4:1] that co rresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 3: excessive zero count interrupt enable (exzcie) ? this bit enables an interrupt if the line.rsrl .exzcl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: bipolar violation interrupt enable (bpvie) ? this bit enables an interrupt if the line.rsrl .bpvl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: bipolar violation count interrupt enable (bpvcie) ? this bit enables an interrupt if the line.rsrl .bpvcl bit and the bit i n gl.isrie .psrie[4:1] that corresponds to this port is set. is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: loss of signal interrupt enable (losie) ? this bit enables an interrupt if the line.rsrl .lo sl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: line.rbpvcr register description: line receive bipolar violat ion count register register address: (0.2.4.6)9ch bit # 15 14 13 12 11 10 9 8 name bpv15 bpv14 bpv13 bpv12 bpv11 bpv10 bpv9 default bpv8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bpv7 bpv6 bpv5 bpv4 bpv3 bpv2 bpv1 default bpv0 0 0 0 0 0 0 0 0 b its 15 to 0: bipolar violation count (bpv[15:0]) ? these sixteen bits indicate the number of bipolar violations detected on the incoming bipolar data stream. this register is updated via the pmu signal (see section 10.4.5 )
ds3170 ds3/e3 single - chip transceiver 155 of 230 register name: line.rexzcr register description: line receive excessive zero count register register address: (0.2.4.6)9eh bit # 15 14 13 12 11 10 9 8 name exz15 exz14 exz13 exz12 exz11 exz10 exz9 default exz8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name exz7 exz6 exz5 exz4 exz3 exz2 exz1 default exz0 0 0 0 0 0 0 0 0 bits 15 to 0: excessive zero count (exz[15:0]) ? these sixteen bits indicate the number of excessive zero conditions detected on the incoming bipolar data stream. this reg ister is updated via the pmu signal (see section 10.4.5 )
ds3170 ds3/e3 single - chip transceiver 156 of 230 12.6 hdlc 12.6.1 hdlc transmit side register map the transmit side utilizes five registers. table 12- 16 . transmit sid e hdlc register map address register register description 0a0h hdlc.tcr hdlc transmit control register 0a2h hdlc.tfdr hdlc transmit fifo data register 0a4h hdlc.tsr hdlc transmit status register 0a6h hdlc.tsrl hdlc transmit status register latched 0a8h hdlc.tsrie hdlc transmit status register interrupt enable 0aah -- unused 0ach -- unused 0aeh -- unused 12.6.1.1 register bit descriptions register name: hdlc.tcr register description: hdlc transmit control register register address: 0a0h bit # 15 14 1 3 12 11 10 9 8 name -- -- -- tdal4 tdal3 tdal2 tdal1 tdal0 default 0 0 0 0 1 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- tpsd tfei tifv tbre tdie tfpd tfrst default 0 0 0 0 0 0 0 0 bits 12 to 8: transmit hdlc data storage available level (tdal[4:0]) ? thes e five bits indicate the minimum number of bytes ([tdal*8}+1) that must be available for storage (do not contain data) in the transmit fifo for hdlc data storage to be available . for example, a value of 21 (15h) results in hdlc data storage being available (thda=1) when the transmit fifo has 169 (a9h) bytes or more available for storage, and hdlc data storage not being available (thda=0) when the transmit fifo has 168 (a8h) bytes or less available for storage. bit 6: transmit packet start disable (tpsd) ? w hen 0, the transmit packet processor will continue sending packets after the current packet end. when 1, the transmit packet processor will stop sending packets after the current packet end. bit 5: transmit fcs error insertion (tfei) ? when 0, the calculat ed fcs (inverted crc - 16) is appended to the packet. when 1, the inverse of the calculated fcs (noninverted crc - 16) is appended to the packet causing an fcs error. this bit is ignored if transmit fcs processing is disabled (tfpd = 1). bit 4: transmit inter - frame fill value (tifv) ? when 0, inter - frame fill is done with the flag sequence (7eh). when 1, inter - frame fill is done with all ?1?s. bit 3: transmit bit reordering enable (tbre) ? when 0, bit reordering is disabled (the first bit transmitted is the lsb of the transmit fifo data byte tfd[0]). when 1, bit reordering is enabled (the first bit transmitted is the msb of the transmit fifo data byte tfd[7]) . bit 2: transmit data inversion enable (tdie) ? when 0, the outgoing data is directly output from packet processing. when 1, the outgoing data is inverted before being output from packet processing.
ds3170 ds3/e3 single - chip transceiver 157 of 230 bit 1: transmit fcs processing disable (tfpd) ? this bit controls whether or not an fcs is calculated and appended to the end of each packet. when 0, the calcula ted fcs bytes are appended to the end of the packet. when 1, the packet is transmitted without an fcs. bit 0: transmit fifo reset (tfrst) ? when 0, the transmit fifo will resume normal operations, however, data is discarded until a start of packet is recei ved after ram power - up is completed. when 1, the transmit fifo is emptied, any transfer in progress is halted, the fifo ram is powered down, and all incoming data is discarded (all tfdr register writes are ignored). register name: hdlc.tfdr register des cription: hdlc transmit fifo data register register address: 0a2h bit # 15 14 13 12 11 10 9 8 name tfd7 tfd6 tfd5 tfd4 tfd3 tfd2 tfd1 tfd0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- -- -- tdpe default 0 0 0 0 0 0 0 0 note: the fifo data and status are loaded into the transmit fifo when the transmit fifo data (tfd[7:0]) is written (upper byte write). when read, the value of these bits is always zero. bits 15 to 8: transmit fifo data (tfd[7:0]) ? these eight bits are the pac ket data to be stored in the transmit fifo. tfd[7] is the msb, and tfd[0] is the lsb. if bit reordering is disabled, tfd[0] is the first bit transmitted, and tfd[7] is the last bit transmitted. if bit reordering is enabled, tfd[7] is the first bit transmit ted, and tfd[0] is the last bit transmitted. bit 0: transmit fifo data packet end (tdpe) ? when 0, the transmit fifo data is not a packet end . when 1, the transmit fifo data is a packet end . register name: hdlc.tsr register description: hdlc transmit s tatus register register address: 0a4h bit # 15 14 13 12 11 10 9 8 name -- -- tffl5 tffl4 tffl3 tffl2 tffl1 tffl0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- tff tfe thda bits 13 to 8: transmit fifo fill level (tffl[5:0]) ? these six bits indicate th e number of eight byte groups available for storage (do not contain data) in the transmit fifo . e.g., a value of 21 (15h) indicates the fifo has 168 (a8h) to 175 (afh) bytes are available for storage. bit 2: transmit fifo full (tff) ? when 0, the transmit fifo contains 255 or less bytes of data . when 1, the transmit fifo is full . bit 1: transmit fifo empty (tfe) ? when 0, the transmit fifo contains at least one byte of data . when 1, the transmit fifo is empty . bit 0: transmit hdlc data storage available (th da) ? when 0, the transmit fifo has less storage space available in the transmit fifo than the transmit hdlc data storage available level (tdal[4:0]). when 1, the transmit fifo has the same or more storage space available than the transmit fifo hdlc data s torage available level.
ds3170 ds3/e3 single - chip transceiver 158 of 230 register name: hdlc.tsrl register description: hdlc transmit status register latched register address: 0a6h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- tfol tful -- tpel tfel t hdal bit 5: transmit fifo overflow latched (tfol) ? this bit is set when a transmit fifo overflow condition occurs . bit 4: transmit fifo underflow latched (tful) ? this bit is set when a transmit fifo underflow condition occurs . an underflow condition re sults in a loss of data. bit 3: transmit packet end latched (tpel) ? this bit is set when an end of packet is read from the transmit fifo. bit 1: transmit fifo empty latched (tfel) ? this bit is set when the tfe bit transitions from 0 to 1 . note: this bit is also set when hdlc.tcr.tfrst is deasserted. bit 0: transmit hdlc data available latched (thdal) ? this bit is set when the thda bit transitions from 0 to 1 . note: this bit is also set when hdlc.tcr.tfrst is deasserted. register name: hdlc.tsrie regis ter description: hdlc transmit status register interrupt enable register address: 0a8h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- tfoie tfuie tpeie -- tfeie thdaie default 0 0 0 0 0 0 0 0 bit 5: transmit fifo overflow interrupt enable (tfoie) ? this bit enables an interrupt if the tfol bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt d isabled 1 = interrupt enabled bit 4: transmit fifo underflow interrupt enable (tfuie) ? this bit enables an interrupt if the tful bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set . 0 = interrupt disabled 1 = interrupt enabled bit 3: transmit packet end interrupt enable (tpeie) ? this bit enables an interrupt if the tpel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to th is port is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 159 of 230 bit 2: transmit fifo full interrupt enable (tffie) ? this bit enables an interrupt if the tffl bit is set and the bit in gl.isrie .psrie[4:1] that corr esponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: transmit fifo empty interrupt enable (tfeie) ? this bit enables an interrupt if the tfel bit is set and the bit in gl.isrie .psrie[ 4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: transmit hdlc data available interrupt enable (thdaie) ? this bit enables an interrupt if the thdal bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled 12.6.2 hdlc receive side register map the receive side utilizes five registers. table 12- 17 . receive side hdlc register map address register register description 0b0h hdlc.rcr hdlc receive control register 0b2h -- unused 0b4h hdlc.rsr hdlc receive status register 0b6h hdlc.rsrl hdlc receive status register latched 0b8h hdlc.rsrie hdlc receive sta tus register interrupt enable 0bah -- unused 0bch hdlc.rfdr hdlc receive fifo data register 0beh -- unused 12.6.2.1 register bit descriptions register name: hdlc.rcr register description: hdlc receive control register register address: 0b0h bit # 15 14 13 1 2 11 10 9 8 name -- -- -- rdal4 rdal3 rdal2 rdal1 rdal0 default 0 0 0 0 1 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- rbre rdie rfpd rfrst default 0 0 0 0 0 0 0 0 bits 12 to 8: receive hdlc data available level (rdal[4:0]) ? these five bits indica te the minimum number of eight byte groups that must be stored (contain data) in the receive fifo before hdlc data is considered to be available (rhda=1) . for example, a value of 21 (15h) results in hdlc data being available when the receive fifo contains 168 (a8h) bytes or more. bit 3: receive bit reordering enable (rbre) ? when 0, bit reordering is disabled (the first bit received is in the lsb of the receive fifo data byte rfd[0]). when 1, bit reordering is enabled (the first bit received is in the msb o f the receive fifo data byte rfd[7]) . bit 2: receive data inversion enable (rdie) ? when 0, the incoming data is directly passed on for packet processing. when 1, the incoming data is inverted before being passed on for packet processing. bit 1: receive f cs processing disable (rfpd) ? when 0, fcs processing is performed (the packets have an fcs appended). when 1, fcs processing is disabled (the packets do not have an fcs appended).
ds3170 ds3/e3 single - chip transceiver 160 of 230 bit 0: receive fifo reset (rfrst) ? when 0, the receive fifo will resume no rmal operations, however, data is discarded until a start of packet is received after ram power - up is completed. when 1, the receive fifo is emptied, any transfer in progress is halted, the fifo ram is powered down, the rhda bit is forced low, and all inco ming data is discarded. register name: hdlc.rsr register description: hdlc receive status register register address: 0b4h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- rff rfe rhda bit 2: rec eive fifo full (rff) ? when 0, the receive fifo contains 255 or less bytes of data . when 1, the receive fifo is full . bit 1: receive fifo empty (rfe) ? when 0, the receive fifo contains at least one byte of data . when 1, the receive fifo is empty . bit 0: r eceive hdlc data available (rhda) ? when 0, the receive fifo contains less data than the receive hdlc data available level (rdal[4:0]). when 1, the receive fifo contains the same or more data than the receive hdlc data available level. register name: hdl c.rsrl register description: hdlc receive status register latched register address: 0b6h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- rfol -- rpel rpsl -- rffl rhdal bit 7: receive fifo overflow latched ( rfol) ? this bit is set when a receive fifo overflow condition occurs . an overflow condition results in a loss of data. bit 4: receive packet end latched (rpel) ? this bit is set when an end of packet is stored in the receive fifo. bit 3: receive packet st art latched (rpsl) ? this bit is set when a start of packet is stored in the receive fifo. bit 2: receive fifo full latched (rffl) ? this bit is set when the rff bit transitions from 0 to 1 . bit 0: receive hdlc data available latched (rhdal) ? this bit is set when the rhda bit transitions from 0 to 1 .
ds3170 ds3/e3 single - chip transceiver 161 of 230 register name: hdlc.rsrie register description: hdlc receive status register interrupt enable register address: 0b8h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 b it # 7 6 5 4 3 2 1 0 name rfoie -- -- rpeie rpsie rffie -- rhdaie default 0 0 0 0 0 0 0 0 bit 7: receive fifo overflow interrupt enable (rfoie) ? this bit enables an interrupt if the rfol bit is set and the bit in gl.i srie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 4: receive packet end interrupt enable (rpeie) ? this bit enables an interrupt if the rpel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 3: receive packet start interrupt enable (rpsie) ? this bit enables an interrupt if the rpsl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: receive fifo full interrupt enable (rffie) ? this bit enables an interrupt if the rffl bit is set and the bit i n gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: receive hdlc data available interrupt enable (rhdaie) ? this bit enables an interrupt if the rhdal bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: hdlc.rfdr register description: hdlc receive fifo data register register address: 0bch bit # 15 14 13 12 11 10 9 8 name rfd7 rfd6 rfd5 rfd4 rfd3 rfd2 rfd1 default rfd0 x x x x x x x x bit # 7 6 5 4 3 2 1 0 name -- -- -- -- rps2 rps1 rps0 default rfdv 0 0 0 0 x x x 0 note: the fifo data and status are updated when the receive fifo data (rfd[7:0]) is read (upper byte read). when this register is read eight bits at a time, a read of the lower byte will reflect the status of the next read of the upper byte, and reading the upper byte when rfdv=0 may result in a lo ss of data. bits 15 to 8: receive fifo data (rfd[7:0]) ? these eight bits are the packet data stored in the receive fifo. rfd[7] is the msb, and rfd[0] is the lsb. if bit reordering is disabled, rfd[0] is the first bit received, and rfd[7] is the last bit received. if bit reordering is enabled, rfd[7] is the first bit received, and rfd[0] is the last bit received.
ds3170 ds3/e3 single - chip transceiver 162 of 230 bits 3 to 1: receive packet status (rps[2:0]) ? these three bits indicate the status of the received packet and packet data . 000 = packet middle 001 = packet start. 010 = reserved 011 = reserved 100 = packet end: good packet 101 = packet end: fcs errored packet. 110 = packet end: invalid packet (a noninteger number of bytes). 111 = packet end: aborted packet. bit 0: receive fifo data valid (rfdv) ? when 0, the receive fifo data (rfd[7:0]) is invalid (the receive fifo is empty) . when 1, the receive fifo data (rfd[7:0]) is valid .
ds3170 ds3/e3 single - chip transceiver 163 of 230 12.7 feac controller 12.7.1 feac transmit side register map the transmit side utilizes five registers. table 12- 18 . feac transmit side register map address register register description 0c0h feac.tcr feac transmit control register 0c2h feac.tfdr feac transmit data register 0c4h feac.tsr feac transmit status register 0c6h feac.tsrl f eac transmit status register latched 0c8h feac.tsrie feac transmit status register interrupt enable 0cah -- unused 0cch -- unused 0ceh -- unused 12.7.1.1 register bit descriptions register name: feac.tcr register description: feac transmit control register register address: 0c0h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 1 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- tfcl tfs1 tfs0 default 0 0 0 0 0 0 0 0 bit 2: transmit feac codeword load (tfcl) ? a 0 to 1 transit ion on this bit loads the transmit feac processor mode select bits (tfs[1:0]), and transmit feac codes (tfca[5:0] and tfcb[5:0]). note: whenever a feac codeword is loaded, any current feac codeword transmission in progress will be immediately halted, and t he new feac codeword transmission will be started based on the new values for tfs[1:0], tfca[5:0], and tfcb[5:0].. bits 1 to 0: transmit feac codeword select (tfs[1:0]) ? these two bits control the transmit feac processor mode. the tfcl bit loads the mode set by this bit. 00 = idle (all ones) 01 = single code (send code tfca ten times and send all ones) 10 = dual code (send code tfca ten times, send code tfcb ten times, and send all ones) 11 = continuous code (send code tfca continuously)
ds3170 ds3/e3 single - chip transceiver 164 of 230 register na me: feac.tfdr register description: transmit feac data register register address: 0c2h bit # 15 14 13 12 11 10 9 8 name -- -- tfcb5 tfcb4 tfcb3 tfcb2 tfcb1 tfcb0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- tfca5 tfca4 tfca3 tfca2 tfca 1 tfca0 default 0 0 0 0 0 0 0 0 bits 13 to 8: transmit feac code b (tfcb[5:0]) ? these six bits are the transmit feac code b data to be stored inserted into codeword b. tfcb[5] is the lsb (last bit transmitted) of the feac code (c[6]), and tfcb[0] is th e msb (first bit transmitted) of the feac code (c[1]). bits 5 to 0: transmit feac code a (tfca[5:0]) ? these six bits are the transmit feac code a data to be stored inserted into codeword a. tfca[5] is the lsb (last bit transmitted) of the feac code (c[6]) , and tfca[0] is the msb (first bit transmitted) of the feac code (c[1]). register name: feac.tsr register description: feac transmit status register register address: 0c4h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- -- -- tfi bit 0: transmit feac idle (tfi) ? when 0, the transmit feac processor is sending a feac codeword. when 1, the transmit feac processor is sending an idle signal (all ones). register name: feac.tsrl register descripti on: feac transmit status register latched register address: 0c6h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- -- -- tfil bit 0: transmit feac idle latched (tfil) ? this bit is set when the tfi bit transitions from 0 to 1 . note: immediately after a reset, this bit will be set to one.
ds3170 ds3/e3 single - chip transceiver 165 of 230 register name: feac.tsrie register description: feac transmit status register interrupt enable register address: 0c8h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- -- -- tfiie default 0 0 0 0 0 0 0 0 bit 0: transmit feac idle interrupt enable (tfiie) ? this bit enables an interrupt if the tfil bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled 12.7.2 feac receive side register map the receive side utilizes five registers. table 12- 19 . feac receive side register map address register register description 0d0h feac.rcr feac receive control register 0d2h -- unused 0d4h feac.rsr feac receive status register 0d6h feac.rsrl feac receive status register latched 0d8h feac .rsrie feac receive status register interrupt enable 0dah -- unused 0dch feac.rfdr feac receive fifo data register 0deh -- unused 12.7.2.1 register bit descriptions register name: feac.rcr register description: feac receive control register register address: 0d0h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 1 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- -- -- rfr default 0 0 0 0 0 0 0 0 bit 0: receive feac reset (rfr) ? when 0, the receive feac processor and receive fea c fifo will resume normal operations. when 1, the receive feac controller is reset. the feac fifo is emptied, any transfer in progress is halted, and all incoming data is discarded.
ds3170 ds3/e3 single - chip transceiver 166 of 230 register name: feac.rsr register description: feac receive status regi ster register address: 0d4h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- rffe rfcd rfi bit 3: receive feac fifo empty (rffe) ? when 0, the receive fifo contains at least one code . when 1, the r eceive fifo is empty . bit 1: receive feac codeword detect (rfcd) ? when 0, the receive feac processor is not currently receiving a feac codeword . when 1, the receive feac processor is currently receiving a feac codeword . bit 0: receive feac idle (rfi) ? wh en 0, the receive feac processor is not receiving a feac idle signal (all ones). when 1, the receive feac processor is receiving a feac idle signal. register name: feac.rsrl register description: feac receive status register latched register address: 0d 6h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- rffol rfcdl rfil bit 2: receive feac fifo overflow latched (rffol) ? this bit is set when a receive fifo overflow condition occurs . an overflow co ndition results in a loss of data. bit 1: receive feac codeword detect latched (rfcdl) ? this bit is set when the rfcd bit transitions from 0 to 1. bit 0: receive feac idle latched (rfil) ? this bit is set when the rfi bit transitions from 0 to 1 . note: immediately after a reset, this bit will be set to one. register name: feac.rsrie register description: feac receive status register interrupt enable register address: 0d8h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- rffoie rfcdie rfiie default 0 0 0 0 0 0 0 0 bit 2: receive feac fifo overflow interrupt enable (rffoie) ? this bit enables an interrupt if the rffol bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 167 of 230 bit 1: receive feac codeword detect interrupt enable (rfcdie) ? this bit enables an interrupt if the rfcdl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: receive feac idle interrupt enable (rfiie) ? this bit enables an interrupt if the rfil bit is set and th e bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: feac.rfdr register description: feac receive fifo data register register address : 0dch bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- rffi rff5 rff4 rff3 rff2 rff1 default rff0 0 0 0 0 0 0 0 0 bit 7: receive feac fifo data invalid (rffi) ? when 0, the receive fi fo data (rff[5:0]) is valid . when 1, the receive fifo data is invalid (receive fifo is empty) . bits 5 to 0: receive feac fifo data (rff[5:0]) ? these six bits are the feac code data stored in the receive fifo. rff[5] is the lsb (last bit received) of the f eac code (c[6]), and rff[0] is the msb (first bit received) of the feac code (c[1]). the receive feac fifo data (rff[5:0]) is updated when it is read (lower byte read).
ds3170 ds3/e3 single - chip transceiver 168 of 230 12.8 trail trace 12.8.1 trail trace transmit side the transmit side utilizes three registers. t able 12- 20 . transmit side trail trace register map address register register description 0e8h tt.tcr trail trace transmit control register 0eah tt.ttiar trail trace transmit identifier address register 0 ech tt.tir trail trace transmit identifier register 0eeh -- unused 12.8.1.1 register bit descriptions register name: tt.tcr register description: trail trace transmit control register register address: 0e8h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- - - -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- reserved tmad tidle tdie tbre default 0 0 0 0 0 0 0 0 bit 3: transmit multiframe alignment insertion disable (tmad) ? when 0, multiframe alignment signal (mas) insertion is enabled, and the first bit transmitted of each trail trace byte is overwritten with an mas bit. wh en 1 , mas insertion is disabled, and the trail trace bytes from the transmit data storage are output without being modified. bit 2: transmit trail trace identifier id le (tidle) ? when 0, the programmed transmit trail trace identifier will be transmitted. when 1, all zeros will be transmitted. bit 1: transmit data inversion enable (tdie) ? when 0, the outgoing data from trail trace processing is output directly. when 1, the outgoing data from trail trace processing is inverted before being output. bit 0: transmit bit reordering enable (tbre) ? when 0, bit reordering is disabled (the first bit transmitted is the msb tt.tir .ttd[7] of the byte) . when 1, bit reordering is en abled (the first bit transmitted is the lsb tt.tir .ttd[0] of the byte).
ds3170 ds3/e3 single - chip transceiver 169 of 230 register name: tt.ttiar register description: trail trace transmit identifier address register register address: 0eah bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- d efault 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- reserved reserved ttia3 ttia2 ttia1 ttia0 default 0 0 0 0 0 0 0 0 bits 3 to 0: transmit trail trace identifier address (ttia[3:0]) ? these four bits indicate the transmit trail trace identifier byte to be read/written by the next memory access. address 0h indicates the first byte of the transmit trail trace identifier. note: the value of these bits increments with each transmit trail trace identifier memory access (when these bits are fh, a memor y access will return them to 0h). register name: tt.tir register description: trail trace transmit identifier register register address: 0ech bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name ttd7 ttd6 ttd5 ttd4 ttd3 ttd2 ttd1 ttd0 default 0 0 0 0 0 0 0 0 bits 7 to 0: transmit trail trace identifier data (ttd[7:0]) ? these eight bits are the transmit trail trace identifier data. the transmit trail trace identifier address will be increm ented whenever these bits are read or written (when address location fh is read or written, the address will return to 0h). 12.8.2 trail trace receive side register map the receive side utilizes seven registers. table 12- 21 . trail trace receive side register map address register register description 0f0h tt.rcr trail trace receive control register 0f2h tt.rtiar trail trace receive identifier address register 0f4h tt.rsr trail trace receive status register 0f6h tt.rsrl trail trace receive status register latched 0f8h tt.rsrie trail trace receive status register interrupt enable 0fah -- unused 0fch tt.rir trail trace receive identifier register 0feh tt.eir trail trace expected identifier register
ds3170 ds3/e3 single - chip transceiver 170 of 230 12.8.2.1 register bi t descriptions register name: tt.rcr register description: trail trace receive control register register address: 0f0h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- reserved rese rved rmad retce rdie rbre default 0 0 0 0 0 0 0 0 bit 3: receive multiframe alignment disable (rmad) ? when 0, multiframe alignment is performed. wh en 1, multiframe alignment is disabled and the trail trace bytes are stored starting with a random byte. bit 2: receive expected trail trace comparison enable (retce) ? when 0, expected trail trace comparison is disabled. wh en 1, expected trail trace comparison is performed. note: when the rmad bit is one, expected trail trace comparison is disabled regardles s of the setting of this bit. bit 1: receive data inversion enable (rdie) ? when 0, the incoming data is directly passed on for trail trace processing. when 1, the incoming data is inverted before being passed on for trail trace processing. bit 0: receive bit reordering enable (rbre) ? when 0, bit reordering is disabled (the first bit received is the msb tt.rir .rtd[7] of the byte) . when 1, bit reordering is enabled (the first bit received is the lsb tt.rir .rtd[0] of the byte). register name: tt.rtiar reg ister description: trail trace receive identifier address register register address: 0f2h bit # 15 14 13 12 11 10 9 8 name -- -- reserved reserved etia3 etia2 etia1 etia0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- reserved reserved rt ia3 rtia2 rtia1 rtia0 default 0 0 0 0 0 0 0 0 bits 11 to 8: expected trail trace identifier address (etia[3:0]) ? these four bits indicate the expected trail trace identifier byte to be read/written by the next memory access. address 0h indicates the fi rst byte of the expected trail trace identifier. note: the value of these bits increments with each expected trail trace identifier memory access (when these bits are fh, a memory access will return them to 0h). bits 3 to 0: receive trail trace identifier address (rtia[3:0]) ? these four bits indicate the receive trail trace identifier byte to be read by the next memory access. address 0h indicates the first byte of the receive trail trace identifier. note: the value of these bits increments with each recei ved trail trace identifier memory access (when these bits are fh, a memory access will return them to 0h).
ds3170 ds3/e3 single - chip transceiver 171 of 230 register name: tt.rsr register description: trail trace receive status register register address: 0f4h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- -- rtim rtiu ridl bit 2: receive trail trace identifier mismatch (rtim) 0 = received and expected trail trace identifiers match. 1 = received and expected trail trace identifiers do not match; trail trace identifier mismatch (tim) declared. bit 1: receive trail trace identifier unstable (rtiu) 0 = received trail trace identifier is not unstable 1 = received trail trace identifier is in an unstable condition (tiu); tiu is declared when eight co nsecutive trail trace identifiers are received that do not match either the receive trail trace identifier or the previously stored current trail trace identifier. bit 0: receive trail trace identifier idle (ridl) 0 = received trail trace identifier is no t in idle condition. 1 = received trail trace identifier is in idle condition. idle condition is declared upon the reception of an all zeros trail trace identifier five consecutive times. register name: tt.rsrl register description: trail trace receive status register latched register address: 0f6h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- rticl rtiml rtiul ridll bit 3: receive trail trace identifier change latched (rticl) ? this bit is set when the receive trail trace identifier is updated . bit 2: receive trail trace identifier mismatch latched (rtiml) ? this bit is set when the tt.rsr .rtim bit transitions from 0 to 1 . bit 1: receive trail trace identifier unstable latched (rtiul) ? this bit is set when the tt.rsr .rtiu bit transitions from 0 to 1 . bit 0: receive trail trace identifier idle latched (ridll) ? this bit is set when the tt.rsr .ridl bit transitions from 0 to 1.
ds3170 ds3/e3 single - chip transceiver 172 of 230 register name: tt.rsrie register description: trail trace receive st atus register interrupt enable register address: 0f8h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- rticie rtimie rtiuie ridlie default 0 0 0 0 0 0 0 0 bit 3: receive trai l trace identifier change interrupt enable (rticie) ? this bit enables an interrupt if the tt.rsrl .rticl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: receive trail trace identifier mismatch interrupt enable (rtimie) ? this bit enables an interrupt if the tt.rsrl .rtiml bit is set and the bit in gl.isrie .psrie[4:1] that corresponds t o this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: receive trail trace identifier unstable interrupt enable (rtiuie) ? this bit enables an interrupt if the tt.rsrl .rtiul bit is set and the bit in gl. isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: receive trail trace identifier idle interrupt enable (ridlie) ? this bit enables an interrupt if the tt.rsrl .ridll bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: tt.rir register description: trail trace receive identifier register register address: 0fch bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rtd7 rtd6 rtd5 rtd4 rtd3 rtd2 rtd1 default rtd0 0 0 0 0 0 0 0 0 bits 7 to 0: receive trail trace identifier data (rtd[7:0]) ? these eight bits are the receive trail trace identifier data. the receive trail trace identifier address will be incremented whenever these bits are read (when byte fh is read, the address will return to 0h).
ds3170 ds3/e3 single - chip transceiver 173 of 230 register name: tt.eir register description: trail trace expected identifier register register address: 0feh bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name etd7 etd6 etd5 etd4 etd3 etd2 etd1 etd0 default 0 0 0 0 0 0 0 0 bits 7 to 0: ex pected trail trace identifier data (etd[7:0]) ? these eight bits are the expected trail trace identifier data. the expected trail trace identifier address will be incremented whenever these bits are read or written (when byte fh is read or written, the add ress will return to 0h).
ds3170 ds3/e3 single - chip transceiver 174 of 230 12.9 ds3/e3 framer 12.9.1 transmit ds3 the transmit ds3 utilizes two registers. table 12- 22 . transmit ds3 framer register map address register register description 118h t3.tcr t3 trans mit control register 11ah t3.teir t3 transmit error insertion register 11ch -- reserved 11eh -- reserved 12.9.1.1 register bit descriptions register name: t3.tcr register description: t3 transmit control register register address: 118h bit # 15 14 13 12 1 1 10 9 8 name -- -- -- pbge tidle cbgd -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- tfebe afebed trdi ardid tfgd tais default 0 0 0 0 0 0 0 0 bit 12: p - bit generation enable (pbge) ? when 0, if transmit frame generation is disable d, transmit frame processor p - bit generation is disabled. the p - bit overhead periods in the incoming t3 signal will be passed through to error insertion. when 1, transmit frame processor p - bit generation is enabled. the p - bit overhead periods in the incomi ng t3 signal will be overwritten even if transmit frame generation is disabled. bit 11: transmit ds3 idle signal (tidle) ? 0 = transmit ds3 idle signal is not inserted 1 = transmit ds3 idle signal is inserted into the ds3 frame. bit 10: c - bit generation d isable (cbgd) (m23 mode only) ? when 0, transmit frame processor c - bit generation is enabled. the c - bit overhead periods in the incoming m23 ds3 signal will be overwritten with zeros . when 1, transmit frame processor c - bit generation is disabled. the c- bit overhead periods in the incoming m23 ds3 signal will be treated as payload, and passed through to overhead insertion. this bit is ignored in c - bit ds3 mode . bit 5: transmit febe error (tfebe) ? when automatic far - end block error generation is defeated (af ebed = 1), the inverse of this bit is inserted into the bits c 41 , c 42 , and c 43 . note: a far - end block error value of zero (tfebe=1) indicates a far - end block error. this bit is ignored in m23 ds3 mode. bit 4: automatic febe defeat (afebed) ? when 0, a far - end block error is automatically generated based upon the receive c - bit parity errors or framing errors. when 1, a far - end block error is inserted from the register bit tfebe . this bit is ignored in m23 ds3 mode . bit 3: transmit rdi alarm (trdi) ? when aut omatic rdi generation is defeated (ardid = 1), the inverse of this bit is inserted into the x - bits (x 1 and x 2 ) . note: an rdi value of zero (trdi=1) indicates an alarm . bit 2: automatic rdi defeat (ardid) ? when 0, the rdi is automatically generated based r eceived ds3 alarms. when 1, the rdi is inserted from the register bit trdi.
ds3170 ds3/e3 single - chip transceiver 175 of 230 bit 1: transmit frame generation disabled (tfgd) ? 0 = transmit frame generation is enabled 1 = transmit frame generation is disabled; ds3 overhead positions in the incoming ds3 payload will be passed through to error insertion. note: frame generation will still overwrite the p - bits if pbge = 1. also, the ds3 overhead periods can still be overwritten by error insertion, overhead insertion, or ais/idle generation. bit 0: transmit alarm indication signal (tais) ? 0 = transmit alarm indication signal is not inserted 1 = transmit alarm indication signal is inserted into data stream payload register name: t3.teir register description: t3 transmit error insertion register register address: 11ah bit # 15 14 13 12 11 10 9 8 name -- -- -- -- ccpeie cpei cfbeie fbei default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name reserved cpeie pei feic1 feic0 fei tsei meims default 0 0 0 0 0 0 0 0 bit 11: continuous c - bit parity error ins ertion enable (ccpeie) ? when 0, single c - bit parity error insertion is enabled . when 1, continuous c - bit parity error insertion is enabled, and c - bit parity errors will be transmitted continuously if cpei is high . bit 10: c - bit parity error insertion enab le (cpei) ? when 0, c - bit parity error insertion is disabled. when 1, c- bit parity error insertion is enabled. bit 9: continuous far - end block error insertion enable (cfbeie) ? when 0, single far - end block error insertion is enabled . when 1, continuous far - end block error insertion is enabled, and far - end block errors will be transmitted continuously if fbei is high . bit 8: far - end block error insertion enable (fbei) ? when 0, far - end block error insertion is disabled. when 1, far - end block error insertion is enabled. bit 6: continuous p - bit parity error insertion enable (cpeie) ? when 0, single p - bit parity error insertion is enabled . when 1, continuous p- bit parity error insertion is enabled, and p - bit parity errors will be transmitted continuously if pei is high . bit 5: p - bit parity error insertion enable (pei) ? when 0, p - bit parity error insertion is disabled. when 1, p - bit parity error insertion is enabled. bits 4 to 3: framing error insertion control (feic[1:0]) ? these two bits control the framing err or event to be inserted. 00 = f - bit error. 01 = m - bit error. 10 = sef error. 11 = oomf error. bit 2: framing error insertion enable (fei) ? when 0, framing error insertion is disabled. when 1, framing error insertion is enabled. bit 1: transmit single erro r insert (tsei) ? this bit causes an error of the enabled type(s) to be inserted in the transmit data stream if manual error insertion is disabled (meims = 0) . a 0 to 1 transition causes a single error to be inserted. for a second error to be inserted, thi s bit must be set to 0, and back to 1. note: if meims is low, and this bit transitions more than once between error insertion opportunities, only one error will be inserted.
ds3170 ds3/e3 single - chip transceiver 176 of 230 bit 0: manual error insert mode select (meims) ? when 0, error insertion is initi ated by the tsei register bit. when 1, error insertion is initiated by the transmit manual error insertion signal (tmei). note: if tmei or tsei is one, changing the state of this bit may cause an error to be inserted. 12.9.2 receive ds3 register map the receive ds3 utilizes eleven registers. two registers are shared for c - bit and m23 ds3 modes. the m23 ds3 mode does not use the rfeber or rcpecr count registers. table 12- 23 . receive ds3 framer register map address re gister register description 120h t3.rcr t3 receive control register 122h -- reserved 124h t3.rsr1 t3 receive status register #1 126h t3.rsr2 t3 receive status register #2 128h t3.rsrl1 t3 receive status register latched #1 12ah t3.rsrl2 t3 receive st atus register latched #2 12ch t3.rsrie1 t3 receive status register interrupt enable #1 12eh t3.rsrie2 t3 receive status register interrupt enable #2 130h -- reserved 132h -- reserved 134h t3.rfecr t3 receive framing error count register 136h t3.rpecr t3 receive p - bit parity error count register 138h t3.rfbecr t3 receive far - end block error count register 13ah t3.rcpecr t3 receive c - bit parity error count register 13ch -- unused 13eh -- unused 12.9.2.1 register bit descriptions register name: t3.rcr regi ster description: t3 receive control register register address: 120h bit # 15 14 13 12 11 10 9 8 name reserved covhd maod mdaisi aaisd ecc fecc1 fecc0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name raile raild raiod raiad romd lip1 lip0 frsync default 0 0 0 0 0 0 0 0 bit 14: c - bit overhead masking disable (covhd) ? when 0, the c - bit positions will be marked as overhead (rden=0) . when 1, the c - bit positions will be marked as data (rden=1) . this bit is ignored in c - bit ds3 mode or w hen the romd bit is set to one. bit 13: multiframe alignment oof disable (maod) ? when 0, an oof condition is declared whenever an oomf or sef condition is declared . when 1, an oof condition is declared only when an sef condition is declared . bit 12: manual downstream ais insertion (mdaisi) ? when 0, manual downstream ais insertion is disabled . when 1, manual downstream ais insertion is enabled .
ds3170 ds3/e3 single - chip transceiver 177 of 230 bit 11: automatic downstream ais disable (aaisd) ? when 0, the presence of an los, oof, or ais condition will cause downstrea m ais to be inserted . when 1, the presence of an los, oof, or ais condition will not cause downstream ais to be inserted . bit 10: error count control (ecc) ? when 0, framing errors, p - bit parity errors, c- bit parity errors, and far - end block errors will no t be counted if an oof or ais condition is present . p- bit parity errors, c- bit parity errors, and far - end block errors will also not be counted during the ds3 frame in which an oof condition is terminated, and the next ds3 frame. when 1, framing errors, p- bit parity errors, c- bit parity errors, and far - end block errors will be counted regardless of the presence of an oof or ais condition. bits 9 to 8: framing error count control (fecc[1:0]) ? these two bits control the type of framing error events that a re counted. 00 = count oof occurrences (counted regardless of the setting of the ecc bit). 01 = count m bit and f bit errors. 10 = count only f bit errors. 11 = count only m bit errors. bit 7: receive alarm indication on lof enable (raile) ? when 0, an lof condition does not affect the receive alarm indication signal (rai). when 1, an lof condition will cause the transmit ds3 x - bits to be set to zero if transmit automatic rdi is enabled. bit 6: receive alarm indication on los disable (raild) ? when 0, an lo s condition will cause the transmit ds3 x - bits to be set to zero if transmit automatic rdi is enabled. when 1, an los condition does not affect the rai signal. bit 5: receive alarm indication on sef disable (raiod) ? when 0, an sef condition will cause the transmit ds3 x - bits to be set to zero if transmit automatic rdi is enabled. when 1, an sef condition does not affect the rai signal. bit 4: receive alarm indication on ais disable (raiad) ? when 0, an ais condition will cause the transmit ds3 x - bits to be set to zero if transmit automatic rdi is enabled. when 1, an ais condition does not affect the rai signal. bit 3: receive overhead masking disable (romd) ? when 0, the ds3 overhead positions in the outgoing ds3 payload will be marked as overhead by rden. when 1, the ds3 overhead positions in the outgoing ds3 payload will be marked as data by rden. when this bit is set to one, the covhd bit is ignored. bits 2 to 1: lof integration period (lip[1:0]) ? these two bits determine the oof integration period for d eclaring lof . 00 = oof is integrated for 3 ms before declaring lof 01 = oof is integrated for 2 ms before declaring lof 10 = oof is integrated for 1 ms before declaring lof. 11 = lof is declared at the same time as oof. bit 0: force framer resynchronizat ion (frsync) ? a 0 to 1 transition forces an oof, sef, and oomf condition. the bit must be cleared and set to one again to force another resynchronization note: the oomf condition is created by failing the most recent four data path m - bit checks. register name: t3.rsr1 register description: t3 receive status register #1 register address: 124h bit # 15 14 13 12 11 10 9 8 name reserved -- reserved reserved t3fm aic idle rua1 bit # 7 6 5 4 3 2 1 0 name oomf -- sef lof rdi ais oof los bit 11: t3 fram ing format mismatch (t3fm) ? t his bit indicates the ds3 framer is programmed for a framing format (c - bit or m23) that is different than the format indicated by the aic bit in the incoming ds3 signal.
ds3170 ds3/e3 single - chip transceiver 178 of 230 bit 10: application identification channel (aic) ? t his bit indicates the current state of the application identification channel (aic) from the c 11 bit. a one indicates c - bit format and a zero indicates m23 format. bit 9: ds3 idle signal (idle) ? when 0, the receive frame processor is not in a ds3 idle signal (idle) condition. when 1, the receive frame processor is in an idle condition. bit 8: receive unframed all 1?s (rua1) ? when 0, the receive frame processor is not in a receive unframed all 1?s (rua1) condition. when 1, the receive frame processor is in an rua1 condition. bit 7: out of multiframe (oomf) ? when 0, the receive frame processor is not in an out of multiframe (oomf) condition. when 1, the receive frame processor is in an oomf condition. bit 6: severely errored frame (sef) ? when 0, the receive f rame processor is not in a severely errored frame (sef) condition. when 1, the receive frame processor is in an sef condition. bit 4: loss of frame (lof) ? when 0, the receive framer is not in a loss of frame (lof) condition. when 1, the receive frame proc essor is in an lof condition. bit 3: remote defect indication (rdi) ? this bit indicates the current state of the remote defect indication (rdi) bit 2: alarm indication signal (ais) ? when 0, the receive frame processor is not in an alarm indication signal (ais) condition. when 1, the receive frame processor is in an ais condition. bit 1: out of frame (oof) ? when 0, the receive framer is not in an out of frame (oof) condition. when 1, the receive frame processor is in an oof condition. bit 0: loss of signa l (los) ? when 0, the receive framer is not in a loss of signal (los) condition. when 1, the receive framer is in an los condition. register name: t3.rsr2 register description: t3 receive status register #2 register address: 126h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- cpec fbec pec fec bit 3: c - bit parity error count (cpec) ? when 0, the c - bit parity error count is zero . when 1, the c - bit parity error count is one or more. this bit is set t o zero in m23 ds3 mode. bit 2: remote error indication count (fbec) ? when 0, the remote error indication count is zero . when 1, the remote error indication count is one or more. this bit is set to zero in m23 ds3 mode. bit 1: p - bit parity error count (pe c) ? when 0, the p - bit parity error count is zero . when 1, the p - bit parity error count is one or more. bit 0: framing error count (fec) ? when 0, the framing error count is zero . when 1, the framing error count is one or more. the type of framing error e vent counted is determined by t3.rcr .fecc[1:0]
ds3170 ds3/e3 single - chip transceiver 179 of 230 register name: t3.rsrl1 register description: t3 receive status register latched #1 register address: 128h bit # 15 14 13 12 11 10 9 8 name reserved reserved rese rved reserved t3fml aicl idlel rua1l bit # 7 6 5 4 3 2 1 0 name oomfl sefl cofal lofl rail aisl oofl losl bit 11: t3 framing format mismatch latched (t3fml) ? this bit is set when the t3fm bit transitions from zero to one. bit 10: application identifi cation channel change latched (aicl) ? this bit is set when the aic bit changes state. bit 9: ds3 idle signal change latched (idlel) ? this bit is set when the idle bit changes state. bit 8: receive unframed all 1?s change latched (rua1l) ? this bit is set when the rua1 bit changes state. bit 7: out of multiframe change latched (oomfl) ? this bit is set when the oomf bit changes state. bit 6: severely errored frame change latched (sefl) ? this bit is set when the sef bit changes state. bit 5: change of fram e alignment latched (cofal) ? this bit is set when the data path frame counters are updated with a new ds3 frame alignment that is different from the previous ds3 frame alignment . bit 4: loss of frame change latched (lofl) ? this bit is set when the lof bi t changes state. bit 3: remote defect indication change latched (rdil) ? this bit is set when the rdi bit changes state. bit 2: alarm indication signal change latched (aisl) ? this bit is set when the ais bit changes state. bit 1: out of frame change latch ed (oofl) ? this bit is set when the oof bit changes state. bit 0: loss of signal change latched (losl) ? this bit is set when the los bit changes state. register name: t3.rsrl2 register description: t3 receive status register latched #2 register addre ss: 12ah bit # 15 14 13 12 11 10 9 8 name -- -- -- -- cpel fbel pel fel bit # 7 6 5 4 3 2 1 0 name -- -- -- -- cpecl fbecl pecl fecl bit 11: c - bit parity error latched (cpel) ? this bit is set when a c - bit parity error is detected . this bit is set to zero in m23 ds3 mode. bit 10: remote error indication latched (fbel) ? this bit is set when a far - end block error is detected . this bit is set to zero in m23 ds3 mode. bit 9: p - bit parity error latched (pel) ? this bit is set when a p - bit parity error i s detected . bit 8: framing error latched (fel) ? this bit is set when a framing error is detected . the type of framing error event that causes this bit to be set is determined by t3.rcr .fecc[1:0] bit 3: c - bit parity error count latched (cpecl) ? this bit is set when the cpec bit transitions from zero to one . this bit is set to zero in m23 ds3 mode .
ds3170 ds3/e3 single - chip transceiver 180 of 230 bit 2: remote error indication count latched (fbecl) ? this bit is set when the fbec bit transitions from zero to one . th is bit is set to zero in m23 ds3 mode . bit 1: p - bit parity error count latched (pecl) ? this bit is set when the pec bit transitions from zero to one. bit 0: framing error count latched (fecl) ? this bit is set when the fec bit transitions from zero to one . register name: t3.rsrie1 register description: t3 receive status register interrupt enable #1 register address: 12ch bit # 15 14 13 12 11 10 9 8 name reserved reserved reserved reserved t3fmie aicie idleie rua1ie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name oomfie sefie cofaie lofie raiie aisie oofie losie default 0 0 0 0 0 0 0 0 bit 11: t3 framing format mismatch interrupt enable (t3fmie) ? this bit enables an interrupt if the t3fml bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 10: application identification channel interrupt enable (aicie) ? this bit enables an interrupt if the aicl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 9: ds3 idle signal change interrupt enable (idleie) ? this bit enables an interrupt if the idlel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 8: receive unframed all 1?s interrupt enable (rua1ie) ? this bit enables an inter rupt if the rua1l bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 7: out of multiframe interrupt enable (oomfie) ? this bit en ables an interrupt if the oomfl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 6: severely errored frame interrupt enable (se fie) ? this bit enables an interrupt if the sefl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 5: change of frame alignment interrupt enable (cofaie) ? this bit enables an interrupt if the cofal bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 4: loss of frame interrupt enable (lofie) ? this bit enables an interrupt if the lofl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 181 of 230 bit 3: remote defect indication interrupt enable (rdiie) ? this bit enables an interrupt if the rdil bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = in terrupt enabled bit 2: alarm indication signal interrupt enable (aisie) ? this bit enables an interrupt if the aisl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrup t disabled 1 = interrupt enabled bit 1: out of frame interrupt enable (oofie) ? this bit enables an interrupt if the oofl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = i nterrupt disabled 1 = interrupt enabled bit 0: loss of signal interrupt enable (losie) ? this bit enables an interrupt if the losl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is se t. 0 = interrupt disabled 1 = interrupt enabled register name: t3.rsrie2 register description: t3 receive status register interrupt enable #2 register address: 12eh bit # 15 14 13 12 11 10 9 8 name -- -- -- -- cpeie fbeie peie feie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- cpecie fbecie pecie fecie default 0 0 0 0 0 0 0 0 bit 11: c - bit parity error interrupt enable (cpeie) ? this bit enables an interrupt if the cpel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 10: remote error interrupt enable (fbeie) ? this bit enables an interrupt if the fbel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 9: p - bit parity error interrupt enable (peie) ? this bit enables an interrupt if the pel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 8: framing error interrupt enable (feie) ? this bit enables an interrupt if the fel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 3: c - bit parity error count interrupt enable (cpecie) ? this bit enables an interrupt if the cpecl bit is se t and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 182 of 230 bit 2: far - end block error count interrupt enable (fbecie) ? this bit enables an interrupt if the fbecl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: p - bit parity error count interrupt enable (pecie) ? this bit e nables an interrupt if the pecl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: framing error count interrupt enable (fecie ) ? this bit enables an interrupt if the fecl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: t3.rfecr register description: t3 receive framing error count register register address: 134h bit # 15 14 13 12 11 10 9 8 name fe15 fe14 fe13 fe12 fe11 fe10 fe9 default fe8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name fe7 fe6 fe5 fe4 fe3 fe2 fe1 default fe0 0 0 0 0 0 0 0 0 bits 15 to 0: framing error count (fe[15:0]) ? these sixteen bits indicate the number of framing error events on the incoming ds3 data stream. this register is updated via the pmu signal (see section 10.4. 5 ) register name: t3.rpecr register description: t3 receive p - bit parity error count register register address: 136h bit # 15 14 13 12 11 10 9 8 name pe15 pe14 pe13 pe12 pe11 pe10 pe9 default pe8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pe7 pe6 pe5 pe4 pe3 pe2 pe1 default pe0 0 0 0 0 0 0 0 0 bits 15 to 0: p - bit parity error count (pe[15:0]) ? these sixteen bits indicate the number of p - bit parity errors detected on the incoming ds3 data stream. this register is updated via the pmu signal ( see section 10.4.5 )
ds3170 ds3/e3 single - chip transceiver 183 of 230 register name: t3.rfbecr register description: t3 receive far - end block error count register register address: 138h bit # 15 14 13 12 11 10 9 8 name fbe fbe 15 fbe 14 fbe 13 fbe 12 fbe 11 fbe 9 10 fbe 8 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name fbe 7 fbe 6 fbe 5 fbe 4 fbe 3 fbe 2 fbe 1 fbe 0 default 0 0 0 0 0 0 0 0 bits 15 to 0: far - end block error count (fbe[15:0]) ? these sixteen bits indicate the number of far - end block errors detect ed on the incoming ds3 data stream . the associated counter will not increment in m23 ds3 mode . this register is updated via the pmu signal (see section 10.4.5 ) register name: t3.rcpecr register description: t 3 receive c - bit parity error count register register address: 13ah bit # 15 14 13 12 11 10 9 8 name cpe15 cpe14 cpe13 cpe12 cpe11 cpe10 cpe9 default cpe8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name cpe7 cpe6 cpe5 cpe4 cpe3 cpe2 cpe1 default cpe0 0 0 0 0 0 0 0 0 bits 15 to 0: c - bit parity error count (cpe[15:0]) ? these sixteen bits indicate the number of c - bit parity errors detected on the incoming ds3 data stream . the associated counter will not increment in m23 ds3 mode . this register is update d via the pmu signal (see section 10.4.5 ) 12.9.3 transmit g.751 e3 the transmit g.751 e3 utilizes two registers. 12.9.3.1 register map table 12- 24 . transmit g.751 e3 framer regist er map address register register description 118h e3g751.tcr e3 g.751 transmit control register 11ah e3g751.teir e3 g.751 transmit error insertion register 11ch -- reserved 11eh -- reserved
ds3170 ds3/e3 single - chip transceiver 184 of 230 12.9.3.2 register bit descriptions register name: e3g751.tcr regi ster description: e3 g.751 transmit control register register address: 118h bit # 15 14 13 12 11 10 9 8 name reserved -- -- reserved reserved reserved tnbc1 tnbc0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- reserved reserved tabc1 tabc 0 tfgd tais default 0 0 0 0 0 0 0 0 bits 9 to 8: transmit n bit control (tnbc[1:0]) ? these two bits control the source of the n bit. 00 = 1 01 = transmit data from hdlc controller. 10 = transmit data from feac controller. 11 = 0 note: if tnbc[1:0] is 10 and tabc[1:0] is 01, both the n bit and a bit will carry the same transmit feac controller (one bit per frame period), however, the n bit and a bit in the same frame may or may not be equal. bits 3 to 2: transmit a bit control (tabc[1:0]) ? these two b its control the source of the a bit. 00 = automatically generated based upon received e3 alarms. 01 = transmit from the feac controller. 10 = 0 11 = 1 note: if tabc[1:0] is 01 and tnbc[1:0] is 10, both the a bit and n bit will carry the same transmit feac controller (one bit per frame period), however, the a bit and n bit in the same frame may or may not be equal. bit 1: transmit frame generation disable (tfgd) ? 0 = transmit frame generation is enabled 1 = transmit frame generation is disabled; e3 overhe ad positions in the incoming e3 payload will be passed through to error insertion. note: the e3 overhead periods can still be overwritten by by error insertion, overhead insertion, or ais generation. bit 0: transmit alarm indication signal (tais) ? when 0 , the normal signal is transmitted . when 1, the output e3 data stream is forced to all ones (ais) .
ds3170 ds3/e3 single - chip transceiver 185 of 230 register name: e3g751.teir register description: e3 g.751 transmit error insertion register register address: 11ah bit # 15 14 13 12 11 10 9 8 name - - -- -- -- reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name reserved reserved reserved feic1 feic0 fei tsei meims default 0 0 0 0 0 0 0 0 bits 4 to 3: framing error insert control (feic[1:0]) ? these two bits c ontrol the framing error event to be inserted. 00 = single bit error in one frame. 01 = word error in one frame. 10 = single bit error in four consecutive frames. 11 = word error in four consecutive frames. bit 2: framing error insertion enable (fei) ? whe n 0, framing error insertion is disabled. when 1, framing error insertion is enabled. bit 1: transmit single error insert (tsei) ? this bit causes an error of the enabled type(s) to be inserted in the transmit data stream if manual error insertion is disab led (meims = 0) . a 0 to 1 transition causes a single error to be inserted. for a second error to be inserted, this bit must be set to 0, and back to 1. note: if meims is low, and this bit transitions more than once between error insertion opportunities, o nly one error will be inserted. bit 0: manual error insert mode select (meims) ? when 0, error insertion is initiated by the tsei register bit. when 1, error insertion is initiated by the transmit manual error insertion signal (tmei). note: if tmei or tsei is one, changing the state of this bit may cause an error to be inserted.
ds3170 ds3/e3 single - chip transceiver 186 of 230 12.9.4 receive g.751 e3 register map the receive g.751 e3 utilizes eight registers. table 12- 25 . receive g.751 e3 framer register map addre ss register register description 120h e3g751.rcr e3 g.751 receive control register 122h -- reserved 124h e3g751.rsr1 e3 g.751 receive status register #1 126h e3g751.rsr2 e3 g.751 receive status register #2 128h e3g751.rsrl1 e3 g.751 receive status r egister latched #1 12ah e3g751.rsrl2 e3 g.751 receive status register latched #2 12ch e3g751.rsrie1 e3 g.751 receive status register interrupt enable #1 12eh e3g751.rsrie2 e3 g.751 receive status register interrupt enable #2 130h -- reserved 132h -- r eserved 134h e3g751.rfecr e3 g.751 receive framing error count register 136h -- reserved 138h -- reserved 13ah -- reserved 13ch -- unused 13eh -- unused 12.9.4.1 register bit descriptions register name: e3g751.rcr register description: e3 g.751 receive con trol register register address: 120h bit # 15 14 13 12 11 10 9 8 name reserved reserved dls mdaisi aaisd ecc fecc1 fecc0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name raile raild raiod raiad romd lip1 lip0 frsync default 0 0 0 0 0 0 0 0 bit 13: receive feac data link source (dls) ? when 0, the receive feac controller will be sourced from the n bit. when 1, the receive feac controller will be sourced from the a bit. bit 12: manual downstream ais insertion (mdaisi) ? when 0, manual downstream ais insertion is disabled . when 1, manual downstream ais insertion is enabled . bit 11: automatic downstream ais disable (aaisd) ? when 0, the presence of an los, oof, or ais condition will cause downstream ais to be inserted . when 1, the presence of an los , oof, or ais condition will not cause downstream ais to be inserted . bit 10: error count control (ecc) ? when 0, framing errors will not be counted if an oof or ais condition is present . when 1, framing errors will be counted regardless of the presence of an oof or ais condition.
ds3170 ds3/e3 single - chip transceiver 187 of 230 bits 9 to 8: framing error count control (fecc[1:0]) ? these two bits control the type of framing error events that are counted. 00 = count oof occurrences (counted regardless of the setting of the ecc bit).. 01 = count each bit e rror in the fas (up to 10 per frame). 10 = count frame alignment signal (fas) errors (up to one per frame). 11 = reserved bit 7: receive alarm indication on lof enable (raile) ? when 0, an lof condition does not affect the receive alarm indication signal ( rai). when 1, an lof condition will cause the transmit e3 a bit to be set to one if transmit automatic rai is enabled. bit 6: receive alarm indication on los disable (raild) ? when 0, an los condition will cause the transmit e3 a bit to be set to one if tr ansmit automatic rai is enabled. when 1, an los condition does not affect the rai signal. bit 5: receive alarm indication on oof disable (raiod) ? when 0, an oof condition will cause the transmit e3 a bit to be set to one if transmit automatic rai is enabl ed. when 1, an oof condition does not affect the rai signal. bit 4: receive alarm indication on ais disable (raiad) ? when 0, an ais condition will cause the transmit e3 a bit to be set to one if transmit automatic rai is enabled. when 1, an ais condition does not affect the rai signal. bit 3: receive overhead masking disable (romd) ? when 0, the e3 overhead positions in the outgoing e3 payload will be marked as overhead by rden. when 1, the e3 overhead positions in the outgoing e3 payload will be marked as data by rden. bits 2 to 1: lof integration period (lip[1:0]) ? these two bits determine the oof integration period for declaring lof . 00 = oof is integrated for 3 ms before declaring lof 01 = oof is integrated for 2 ms before declaring lof. 10 = oof is in tegrated for 1 ms before declaring lof 11 = lof is declared at the same time as oof bit 0: force framer resynchronization (frsync) ? a 0 to 1 transition forces an oof condition at the fas check. this bit must be cleared and set to one again to force anothe r resynchronization. note: the oof condition is created by failing the most recent four data path fas checks. register name: e3g751.rsr1 register description: e3 g.751 receive status register #1 register address: 124h bit # 15 14 13 12 11 10 9 8 name reserved -- reserved reserved reserved reserved reserved rua1 bit # 7 6 5 4 3 2 1 0 name rab -- rnb lof rdi ais oof los bit 8: receive unframed all 1?s (rua1) ? when 0, the receive frame processor is not in a receive unframed all 1?s (rua1) condition . when 1, the receive frame processor is in an rua1 condition. bit 7: receive a bit (rab) ? this bit is the integrated a bit extracted from the e3 frame. bit 6: receive n bit (rnb) ? this bit is the integrated n bit extracted from the e3 frame. bit 4: loss of frame (lof) ? when 0, the receive frame processor is not in a loss of frame (lof) condition. when 1, the receive frame processor is in an lof condition. bit 3: remote alarm indication (rdi) ? this bit indicates the current state of the remote alarm ind ication (rdi). bit 2: alarm indication signal (ais) ? when 0, the receive frame processor is not in an alarm indication signal (ais) condition. when 1, the receive frame processor is in an ais condition.
ds3170 ds3/e3 single - chip transceiver 188 of 230 bit 1: out of frame (oof) ? when 0, the receive fram e processor is not in an out of frame (oof) condition. when 1, the receive frame processor is in an oof condition. bit 0: loss of signal (los) ? when 0, the receive loss of signal (los) input (rlos) is low. when 1, rlos is high. register name: e3g751.rsr 2 register description: e3 g.751 receive status register #2 register address: 126h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- reserved reserved reserved fec bit 0: framing error count (fec) ? w hen 0, the framing error count is zero . when 1, the framing error count is one or more. register name: e3g751.rsrl1 register description: e3 g.751 receive status register latched #1 register address: 128h bit # 15 14 13 12 11 10 9 8 name reserved re served reserved reserved reserved reserved reserved rua1l bit # 7 6 5 4 3 2 1 0 name acl ncl cofal lofl rdil aisl oofl losl bit 8: receive unframed all 1?s change latched (rua1l) ? this bit is set when the rua1 bit changes state. bit 7: a bit change l atched (acl) ? this bit is set when the rab bit changes state. bit 6: n bit change latched (ncl) ? this bit is set when the rnb bit changes state. bit 5: change of frame alignment latched (cofal) ? this bit is set when the data path frame counters are upda ted with a new frame alignment that is different from the previous frame alignment . bit 4: loss of frame change latched (lofl) ? this bit is set when the lof bit changes state. bit 3: remote alarm indication change latched (rdil) ? this bit is set when the rdi bit changes state. bit 2: alarm indication signal change latched (aisl) ? this bit is set when the ais bit changes state. bit 1: out of frame change latched (oofl) ? this bit is set when the oof bit changes state. bit 0: loss of signal change latched (losl) ? this bit is set when the los bit changes state.
ds3170 ds3/e3 single - chip transceiver 189 of 230 register name: e3g751.rsrl2 register description: e3 g.751 receive status register latched #2 register address: 12ah bit # 15 14 13 12 11 10 9 8 name -- -- -- -- reserved reserved reserved fel bit # 7 6 5 4 3 2 1 0 name -- -- -- -- reserved reserved reserved fecl bit 8: framing error latched (fel) ? this bit is set when a framing error is detected . bit 0: framing error count latched (fecl) ? this bit is set when the fec bit transitions fro m zero to one. register name: e3g751.rsrie1 register description: e3 g.751 receive status register interrupt enable #1 register address: 12ch bit # 15 14 13 12 11 10 9 8 name reserved reserved reserved reserved reserved reserved reserved rua1ie def ault 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name acie ncie cofaie lofie rdiie aisie oofie losie default 0 0 0 0 0 0 0 0 bit 8: receive unframed all 1?s interrupt enable (rua1ie) ? this bit enables an interrupt if the rua1l bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 7: a bit change interrupt enable (acie) ? this bit enables an interrupt if the acl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 6: n bit change interrupt enable (ncie) ? this bit enables an interrupt if the ncl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 5: change of frame alignment interrupt enable (cofaie) ? this bit enables an interrupt if the co fal bit and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. set. 0 = interrupt disabled 1 = interrupt enabled bit 4: loss of frame interrupt enable (lofie) ? this bit enables an interrupt i f the lofl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 3: remote alarm indication interrupt enable (rdiie) ? this bit enab les an interrupt if the rdil bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 190 of 230 bit 2: alarm indication signal interrupt enable (aisi e) ? this bit enables an interrupt if the aisl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: out of frame interrupt enabl e (oofie) ? this bit enables an interrupt if the oofl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: loss of signal interr upt enable (losie) ? this bit enables an interrupt if the losl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: e3 g751.rsrie2 register description: e3 g.751 receive status register interrupt enable #2 register address: 12eh bit # 15 14 13 12 11 10 9 8 name -- -- -- -- reserved reserved reserved feie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- reserved reserved reserved fecie default 0 0 0 0 0 0 0 0 bit 8: framing error interrupt enable (feie) ? this bit enables an interrupt if the fel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: framing error count interrupt enable (fecie) ? this bit enables an interrupt if the fecl bit is set and the bit in gl.isrie .psrie[4:1] th at corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: e3g751.rfecr register description: e3 g.751 receive framing error count register register address: 134h bit # 15 14 13 12 11 10 9 8 name fe15 fe14 fe13 fe12 fe11 fe10 fe9 default fe8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name fe7 fe6 fe5 fe4 fe3 fe2 fe1 default fe0 0 0 0 0 0 0 0 0 bits 15 to 0: framing error count (fe[15:0]) ? these sixteen bits indicate the number of framing error events on the i ncoming e3 data stream. this register is updated via the pmu signal (see section 10.4.5 )
ds3170 ds3/e3 single - chip transceiver 191 of 230 12.9.5 transmit g.832 e3 register map the transmit g.832 e3 utilizes four registers. table 12- 26 . transmit g.832 e3 framer register map address register register description 118h e3g832.tcr e3 g.832 transmit control register 11ah e3g832.teir e3 g.832 transmit error insertion register 11ch e3g832.tmabr e3 g.832 transmit ma byte r egister 11eh e3g832.tngbr e3 g.832 transmit nr and gc byte register 12.9.5.1 register bit descriptions register name: e3g832.tcr register description: e3 g.832 transmit control register register address: 118h bit # 15 14 13 12 11 10 9 8 name reserved -- -- reserved reserved tgcc tnrc1 tnrc0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- tfebe afebed trdi ardid tfgd tais default 0 0 0 0 0 0 0 0 bit 10: transmit gc byte control (tgcc) ? when 0, the gc byte is inserted from the transmit hdlc c ontroller . when 1, the gc byte is inserted from the gc byte register. note: if bit tgcc is 0 and tnrc[1:0] is 01, both the gc byte and nr byte will carry the same transmit hdlc controller (eight bits per frame period), however, the gc byte and nr byte in the same frame may or may not be equal. bits 9 to 8: transmit nr byte control (tnrc[1:0]) ? these two bits control the source of the nr byte. 00 = all ones. 01 = transmit from the hdlc controller. 10 = transmit from the feac controller. 11 = nr byte regist er. note: if tnrc[1:0] is 01 and tgcc is 0, both the nr byte and gc byte will carry the same transmit hdlc controller (eight bits per frame period), however, the nr byte and gc byte in the same frame may or may not be equal. bit 5: transmit rei error (tfeb e) ? when automatic rei generation is defeated (afebed = 1), this bit is inserted into the second bit of the ma byte. bit 4: automatic rei defeat (afebed) ? when 0, the rei is automatically generated based upon the transmit remote error indication (trei) s ignal. when 1, the rei is inserted from the register bit tfebe. bit 3: transmit rdi alarm (trdi) ? when automatic rdi generation is defeated (ardid = 1), this bit is inserted into the first bit of the ma byte. bit 2: automatic rdi defeat (ardid) ? when 0, the rdi is automatically generated based upon the received e3 alarms. when 1, the rdi is inserted from the register bit trdi. bit 1: transmit frame generation disabled (tfgd) ? 0 = transmit frame generation is enabled
ds3170 ds3/e3 single - chip transceiver 192 of 230 1 = transmit frame generation is dis abled; e3 overhead positions in the incoming e3 payload will be passed through to error insertion. note: the e3 overhead periods can still be overwritten by by error insertion, overhead insertion, or ais generation. bit 0: transmit alarm indication signal (tais) ? when 0, the normal signal is transmitted . when 1, the e3 output data stream is forced to all ones (ais) . register name: e3g832.teir register description: e3 g.832 transmit error insertion register register address: 11ah bit # 15 14 13 12 11 10 9 8 name -- -- -- -- reserved reserved cfbeie fbei default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pbee cpeie pei feic1 feic0 fei tsei meims default 0 0 0 0 0 0 0 0 bit 9: continuous remote error indication error insertion enable (cfbeie) ? when 0, single remote error indication (rei) error insertion is enabled . when 1, continuous rei error insertion is enabled, and rei errors will be transmitted continuously if fbei is high . bit 8: remote error indication error insertion enable (fbei) ? when 0, rei error insertion is disabled. when 1, rei error insertion is enabled. bit 7: parity block error enable (pbee) ? when 0, a parity error is generated by inverting a single bit in the em byte. when 1, a parity error is generated by inverting all eight bits in the em byte . bit 6: continuous parity error insertion enable (cpeie) ? when 0, single parity (bip - 8) error insertion is enabled . when 1, continuous parity error insertion is enabled, and parity errors will be transmitted continuously if pei is high . bit 5: parity error insertion enable (pei) ? when 0, parity error insertion is disabled. when 1, parity error insertion is enabled. bits 4 to 3: framing error control (feic[1:0]) ? these two bits control the framing error event to be inserted. 00 = singl e bit error in one frame. 01 = word error in one frame. 10 = single bit error in four consecutive frames. 11 = word error in four consecutive frames. bit 2: framing error insertion enable (fei) ? when 0, framing error insertion is disabled. when 1, framing error insertion is enabled. bit 1: transmit single error insert (tsei) ? this bit causes an error of the enabled type(s) to be inserted in the transmit data stream if manual error insertion is disabled (meims = 0) . a 0 to 1 transition causes a single erro r to be inserted. for a second error to be inserted, this bit must be set to 0, and back to 1. note: if meims is low, and this bit transitions more than once between error insertion opportunities, only one error will be inserted. bit 0: manual error inser t mode select (meims) ? when 0, error insertion is initiated by the tsei register bit. when 1, error insertion is initiated by the transmit manual error insertion signal (tmei). note: if tmei or tsei is one, changing the state of this bit may cause an erro r to be inserted.
ds3170 ds3/e3 single - chip transceiver 193 of 230 register name: e3g832.tmabr register description: e3 g.832 transmit ma byte register register address: 11ch bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tpt2 tpt1 t pt0 ttigd tti3 tti2 tti1 tti0 default 0 0 0 0 0 0 0 0 bits 7 to 5: transmit payload type (tpt[2:0]) ? these bits determines the value transmitted in the payload type (third, fourth, and fifth bits in the ma byte). bit 4: transmit timing source indicator bit generation disable (ttigd) ? when 0, the last three bits of the ma byte (ma[6:8]) are generated from the four timing source indicator bits tti[3:0] . when 1, tti[3] is ignored and tti[2:0] are directly inserted into the last three bits of the ma byte . bits 3 to 0: transmit timing source indication (tti[3:0]) ? these four bits make up the timing source indicator bits . register name: e3g832.tngbr register description: e3 g.832 transmit nr and gc byte register register address: 11eh bit # 15 14 13 12 11 10 9 8 name tgc7 tgc6 tgc5 tgc4 tgc3 tgc2 tgc1 tgc0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tnr7 tnr6 tnr5 tnr4 tnr3 tnr2 tnr1 tnr0 default 0 0 0 0 0 0 0 0 bits 15 to 8: transmit gc byte (tgc[7:0]) ? these eight bits are the gc byte to be inserted into the e3 frame. bits 7 to 0: transmit nr byte (tnr[7:0]) ? these eight bits are the nr byte to be inserted into the e3 frame.
ds3170 ds3/e3 single - chip transceiver 194 of 230 12.9.6 receive g.832 e3 register map the receive g.832 e3 utilizes thirteen registers. table 12- 27 . receive g.832 e3 framer register map address register register description 120h e3g832.rcr e3 g.832 receive control register 122h e3g832.rmacr e3 g.832 receive ma byte control register 124h e3g832.rsr1 e3 g.832 receive s tatus register #1 126h e3g832.rsr2 e3 g.832 receive status register #2 128h e3g832.rsrl1 e3 g.832 receive status register latched #1 12ah e3g832.rsrl2 e3 g.832 receive status register latched #2 12ch e3g832.rsrie1 e3 g.832 receive status register inter rupt enable #1 12eh e3g832.rsrie2 e3 g.832 receive status register interrupt enable #2 130h e3g832.rmabr e3 g.832 receive ma byte register 132h e3g832.rngbr e3 g.832 receive nr and gc byte register 134h e3g832.rfecr e3 g.832 receive framing error count register 136h e3g832.rpecr e3 g.832 receive parity error count register 138h e3g832.rfber e3 g.832 receive remote error indication count register 13ah -- reserved 13ch -- unused 13eh -- unused 12.9.6.1 register bit descriptions register name: e3g832.rcr re gister description: e3 g.832 receive control register register address: 120h bit # 15 14 13 12 11 10 9 8 name reserved pec dls mdaisi aaisd ecc fecc1 fecc0 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name raile raild raiod raiad romd lip1 lip0 fr sync default 0 0 0 0 0 0 0 0 bit 14: parity error count (pec) ? when 0, bip - 8 block errors (em byte) are detected (no more than one per frame). when 1, bip -8 - bit errors are detected (up to 8 per frame) . bit 13: receive hdlc data link source (dls) ? when 0, the receive hdlc data link will be sourced from the gc byte. when 1, the receive hdlc data link will be sourced from the nr byte. bit 12: manual downstream ais insertion (mdaisi) ? when 0, manual downstream ais insertion is disabled . when 1, manual do wnstream ais insertion is enabled . bit 11: automatic downstream ais disable (aaisd) ? when 0, the presence of an los, oof, or ais condition will cause downstream ais to be inserted . when 1, the presence of an los, oof, or ais condition will not cause downs tream ais to be inserted . bit 10: error count control (ecc) ? when 0, framing errors, parity errors, and rei errors will not be counted if an oof or ais condition is present . parity errors and rei errors will also not be counted during the e3 frame in whi ch an oof or ais condition is terminated, and the next e3 frame. when 1, framing errors, parity errors, and rei errors will be counted regardless of the presence of an oof or ais condition.
ds3170 ds3/e3 single - chip transceiver 195 of 230 bits 9 to 8: framing error count control (fecc[1:0]) ? these two bits control the type of framing error events that are counted. 00 = count oof occurrences (counted regardless of the setting of the ecc bit).. 01 = count each bit error in fa1 and fa2 (up to 16 per frame). 10 = count frame alignment word (fa1 and fa2) err ors (up to one per frame). 11 = count fa1 byte errors and fa2 byte errors (up to 2 per frame). bit 7: receive alarm indication on lof enable (raile) ? when 0, an lof condition does not affect the receive alarm indication signal (rai). when 1, an lof condit ion will cause the transmit e3 rdi bit to be set to one if transmit automatic rdi is enabled. bit 6: receive alarm indication on los disable (raild) ? when 0, an los condition will cause the transmit e3 rdi bit to be set to one if transmit automatic rdi is enabled. when 1, an los condition does not affect the rai signal. bit 5: receive alarm indication on oof disable (raiod) ? when 0, an oof condition will cause the transmit e3 rdi bit to be set to one if transmit automatic rdi is enabled. when 1, an oof co ndition does not affect the rai signal. bit 4: receive alarm indication on ais disable (raiad) ? when 0, an ais condition will cause the transmit e3 rdi bit to be set to one if transmit automatic rdi is enabled. when 1, an ais condition does not affect the rai signal. bit 3: receive overhead masking disable (romd) ? when 0, the e3 overhead positions in the outgoing e3 payload will be marked as overhead by rden. when 1, the e3 overhead positions in the outgoing e3 payload will be marked as data by rden. bits 2 to 1: lof integration period (lip[1:0]) ? these two bits determine the oof integration period for declaring lof . 00 = oof is integrated for 3 ms before declaring lof. 01 = oof is integrated for 2 ms before declaring lof. 10 = oof is integrated for 1 ms before declaring lof. 11 = lof is declared at the same time as oof. bit 0: force framer resynchronization (frsync) ? a 0 to 1 transition forces. an oof condition at the next framing word check. this bit must be cleared and set to one again to force anothe r resynchronization. note: the oof condition is created by failing the most recent four data path frame alignment word checks. register name: e3g832.rmacr register description: e3 g.832 receive ma byte control register register address: 122h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- ept2 ept1 ept0 tied default 0 0 0 0 0 0 0 0 bits 3 to 1: expected payload type (ept[2:0]) ? these three bits contain the expected value o f the payload type. bit 0: timing source indicator bit extraction disable (tied) ? when 0, the four timing source indications bits are extracted from the last three bits of the ma byte (ma[6:8]) , and stored in a register . when 1, timing source indicator bi t extraction is disabled, and the last three bits of the ma byte are integrated and stored in a register .
ds3170 ds3/e3 single - chip transceiver 196 of 230 register name: e3g832.rsr1 register description: e3 g.832 receive status register #1 register address: 124h bit # 15 14 13 12 11 10 9 8 name -- re served -- rptu rptm reserved reserved rua1 bit # 7 6 5 4 3 2 1 0 name reserved -- reserved lof rai ais oof los bit 12: receive payload type unstable (rptu) ? when 0, the receive payload type is stable. when 1, the receive payload type is unstable. bit 11: receive payload type mismatch (rptm) ? when 0, the receive payload type and expected payload type match. when 1, the receive payload type and expected payload type do not match. bit 8: receive unframed all 1?s (rua1) ? when 0, the receive frame pro cessor is not in a receive unframed all 1?s (rua1) condition. when 1, the receive frame processor is in an rua1 condition. bit 4: loss of frame (lof) ? when 0, the receive frame processor is not in a loss of frame (lof) condition. when 1, the receive frame processor is in an lof condition. bit 3: remote defect indication (rdi) ? this bit indicates the current state of the remote defect indication (rdi). bit 2: alarm indication signal (ais) ? when 0, the receive frame processor is not in an alarm indication signal (ais) condition. when 1, the receive frame processor is in an ais condition. bit 1: out of frame (oof) ? when 0, the receive frame processor is not in an out of frame (oof) condition. when 1, the receive frame processor is in an oof condition. bit 0 : loss of signal (los) ? when 0, the receive loss of signal (los) input (rlos) is low. when 1, rlos is high. register name: e3g832.rsr2 register description: e3 g.832 receive status register #2 register address: 126h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- bit # 7 6 5 4 3 2 1 0 name -- -- -- -- reserved fbec pec fec bit 2: remote error indication count (fbec) ? when 0, the remote error indication count is zero . when 1, the remote error indication count is one or more. bit 1: par ity error count (pec) ? when 0, the parity error count is zero . when 1, the parity error count is one or more. bit 0: framing error count (fec) ? when 0, the framing error count is zero . when 1, the framing error count is one or more.
ds3170 ds3/e3 single - chip transceiver 197 of 230 register name: e3g8 32.rsrl1 register description: e3 g.832 receive status register latched #1 register address: 128h bit # 15 14 13 12 11 10 9 8 name reserved -- til rptul rptml rptl reserved rua1l bit # 7 6 5 4 3 2 1 0 name gcl nrl cofal lofl rdil aisl oofl losl b it 13: timing source indication change latched (til) ? this bit is set when the ti[3:0] bits change state. bit 12: receive payload type unstable latched (rptul) ? this bit is set when the rptu bit transitions from zero to one. bit 11: receive payload type mismatch latched (rptml) ? this bit is set when the rptm bit transitions from zero to one. bit 10: receive payload type change latched (rptl) ? this bit is set when the rpt[2:0] bits change state. bit 8: receive unframed all 1?s change latched (rua1l) ? th is bit is set when the rua1 bit changes state. bit 7: gc byte change latched (gcl) ? this bit is set when the rgc byte changes state. bit 6: nr byte change latched (nrl) ? this bit is set when the rnr byte changes state. bit 5: change of frame alignment la tched (cofal) ? this bit is set when the data path frame counters are updated with a new frame alignment that is different from the previous frame alignment . bit 4: loss of frame change latched (lofl) ? this bit is set when the lof bit changes state. bit 3 : remote defect indication change latched (rdil) ? this bit is set when the rdi bit changes state. bit 2: alarm indication signal change latched (aisl) ? this bit is set when the ais bit changes state. bit 1: out of frame change latched (oofl) ? this bit i s set when the oof bit changes state. bit 0: loss of signal change latched (losl) ? this bit is set when the los bit changes state. register name: e3g832.rsrl2 register description: e3 g.832 receive status register latched #2 register address: 12ah b it # 15 14 13 12 11 10 9 8 name -- -- -- -- reserved fbel pel fel bit # 7 6 5 4 3 2 1 0 name -- -- -- -- reserved fbecl pecl fecl bit 10: remote error indication latched (fbel) ? this bit is set when a remote error indication is detected . bit 9: pari ty error latched (pel) ? this bit is set when a bip - 8 parity error is detected. bit 8: framing error latched (fel) ? this bit is set when a framing error is detected . bit 2: remote error indication count latched (fbecl) ? this bit is set when the fbec bit transitions from zero to one. bit 1: parity error count latched (pecl) ? this bit is set when the pec bit transitions from zero to one. bit 0: framing error count latched (fecl) ? this bit is set when the fec bit transitions from zero to one.
ds3170 ds3/e3 single - chip transceiver 198 of 230 register na me: e3g832.rsrie1 register description: e3 g.832 receive status register interrupt enable #1 register address: 12ch bit # 15 14 13 12 11 10 9 8 name reserved -- tiie rptuie rptmie rptie reserved rua1ie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name gcie nrie cofaie lofie raiie aisie oofie losie default 0 0 0 0 0 0 0 0 bit 13: timing indication interrupt enable (tiie) ? this bit enables an interrupt if the til bit is set and the bit in gl.isrie .psrie [4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 12: receive payload type unstable interrupt enable (rptuie) ? this bit enables an interrupt if the rptul bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 11: receive payload type mismatch interrupt enable (rptmie) ? this bit enables an interrupt if the rptml bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 10: receive payload type interrupt enable (rptie) ? this bit enables an interrupt if the rptl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 8: receive unframed all 1?s interrupt enable (rua1ie) ? this bit enables an interrupt if th e rua1l bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 7: gc byte interrupt enable (gcie) ? this bit enables an interrupt if th e gcl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 6: nr byte interrupt enable (nrie) ? this bit enables an interrupt if th e nrl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 5: change of frame alignment interrupt enable (cofaie) ? this bit enable s an interrupt if the cofal bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 4: loss of frame interrupt enable (lofie) ? this b it enables an interrupt if the lofl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 199 of 230 bit 3: remote defect indication interrupt enab le (rdiie) ? this bit enables an interrupt if the rdil bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: alarm indication sig nal interrupt enable (aisie) ? this bit enables an interrupt if the aisl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: ou t of frame interrupt enable (oofie) ? this bit enables an interrupt if the oofl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bi t 0: loss of signal interrupt enable (losie) ? this bit enables an interrupt if the losl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt e nabled register name: e3g832.rsrie2 register description: e3 g.832 receive status register interrupt enable #2 register address: 12eh bit # 15 14 13 12 11 10 9 8 name -- -- -- -- reserved fbeie peie feie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- -- -- -- reserved fbecie pecie fecie default 0 0 0 0 0 0 0 0 bit 10: remote error indication interrupt enable (fbeie) ? this bit enables an interrupt if the fbel bit is set and the bit in gl.isrie . psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 9: parity error interrupt enable (peie) ? this bit enables an interrupt if the pel bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 8: framing error interrupt enable (feie) ? this bit enables an interrupt if the fel bit is set and the bit in gl.isri e .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: remote error indication count interrupt enable (fbecie) ? this bit enables an interrupt if the fbecl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: parity error count interrupt enable (pecie) ? this bit enables an interrupt if the pecl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled
ds3170 ds3/e3 single - chip transceiver 200 of 230 bit 0: framing error count interrupt enable (fecie) ? this bit enables an interrupt if the fecl bit is set and the bit in gl.isrie .psrie[4:1] that corresponds to this port is set. 0 = interrupt disabled 1 = interrupt enabled register name: e3g832.rmabr register description: e3 g.832 receive ma byte register register address: 130h bit # 15 14 13 12 11 10 9 8 name -- -- -- -- -- -- -- -- default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name -- rpt2 rpt1 rpt0 ti3 ti2 ti1 default ti0 0 0 0 0 0 0 0 0 bits 6 to 4: receive payload type (rpt[2:0]) ? these three bits a re the integrated version of the payload type (ma[3:5]) from the ma byte. bits 3 to 0: receive timing source indication (ti[3:0]) ? when timing source indicator extraction is enabled, these four bits are the integrated version of the four timing source ind icator bits extracted from the last three bits of the ma byte (ma[6:8]). when timing source indicator bit extraction is disabled, ti[3] is zero, and ti[2:0] contain the integrated version of the last three bits of the ma byte . register name: e3g832.rngbr register description: e3 g.832 receive nr and gc byte register register address: 132h bit # 15 14 13 12 11 10 9 8 name rgc7 rgc6 rgc5 rgc4 rgc3 rgc2 rgc1 default rgc0 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rnr7 rnr6 rnr5 rnr4 rnr3 rnr2 rnr1 default r nr0 0 0 0 0 0 0 0 0 bits 15 to 8: receive gc byte (rgc[7:0]) ? these eight bits are the integrated version of the gc byte as extracted from the e3 frame. bits 7 to 0: receive nr byte (rnr[7:0]) ? these eight bits are the integrated version of th e nr byte as extracted from the e3 frame.
ds3170 ds3/e3 single - chip transceiver 201 of 230 register name: e3g832.rfecr register description: e3 g.832 receive framing error count register register address: 134h bit # 15 14 13 12 11 10 9 8 name fe15 fe14 fe13 fe12 fe11 fe10 fe9 default fe8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name fe7 fe6 fe5 fe4 fe3 fe2 fe1 default fe0 0 0 0 0 0 0 0 0 bits 15 to 0: framing error count (fe[15:0]) ? these sixteen bits indicate the number of framing error events on the incoming e3 data stream. this register is updated via the pmu signal (see section 10.4.5 ) register name: e3g832.rpecr register description: e3 g.832 receive parity error count register register address: 136h bit # 15 14 13 12 11 10 9 8 name pe15 pe14 pe13 pe12 pe11 pe10 pe9 default pe8 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pe7 pe6 pe5 pe4 pe3 pe2 pe1 default pe0 0 0 0 0 0 0 0 0 bits 15 to 0: parity error count (pe[15:0]) ? these sixteen bits indicate the number of parity (bip - 8) errors detected on the incoming e3 data stream. this register is updated via the pmu signal (see section 10.4.5 ) register name: e3g832.rfber register description: e3 g.832 receive remote error indication count regi ster register address: 138h bit # 15 14 13 12 11 10 9 8 name fbe fbe 15 fbe 14 fbe 13 fbe 12 fbe 11 fbe 9 10 fbe 8 default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name fbe 7 fbe 6 fbe 5 fbe 4 fbe 3 fbe 2 fbe 1 fbe 0 default 0 0 0 0 0 0 0 0 bits 15 to 0: remote er ror indication count (fbe[15:0]) ? these sixteen bits indicate the number of remote error indications detected on the incoming e3 data stream. this register is updated via the pmu signal (see section 10.4.5 )
ds3170 ds3/e3 single - chip transceiver 202 of 230 13 jt ag information 13.1 jtag description this device supports the standard instruction codes sample/preload, bypass, and extest. optional public instructions included are highz, clamp, and idcode. the device contains the following items, which meet the requirement s set by the ieee 1149.1 standard test access port (tap) and boundary scan architecture: test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the test access port has the necess ary interface pins, namely jtclk, jtdi, jtdo, and jtms , and the optional jtrst input . details on these pins can be found in section 8 . refer to ieee 1149.1 - 1990, ieee 1149.1a- 1993, and ieee 1149.1b - 1994 for detai ls about the boundary scan architecture and the test access port. figure 13- 1 . jtag block diagram boundary scan register identification register bypass register instruction register test access port controller mux select tri - sta te jtdi 10k jtms 10k jtclk jtrst 10k jtdo
ds3170 ds3/e3 single - chip transceiver 203 of 230 13.2 jtag tap controller state machine description this section covers the details o n the operation of the test access port (tap) controller state machine. see figure 13-2 for details on each of the states described below. the tap controller is a finite state machine that responds to t he logic level at jtms on the rising edge of jtclk. figure 13- 2 . jtag tap controller state machine test-logic-reset run-test/idle select dr-scan 1 0 capture-dr 1 0 shift-dr 0 1 exit1- dr 1 0 pause-dr 1 exit2-dr 1 update-dr 0 0 1 select ir-scan 1 0 capture-ir 0 shift-ir 0 1 exit1-ir 1 0 pause-ir 1 exit2-ir 1 update-ir 0 0 1 0 0 1 0 1 0 1 test - logic - reset. when jtrst is changed from low to high , the tap controller starts in the test -logi c- reset state, and the instruction register is loaded with the idcode instruction. all system logic and i/o pads on the device operate normally. this state can also be reached from any other state by holding jtms high and clocking jtclk five times. run - te st - idle. run- test - idle is used between scan operations or during specific tests. the instruction register and test register remain idle. select -dr- scan. all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the con troller into the capture - dr state and initiates a scan sequence. jtms high moves the controller to the select - ir - scan state.
ds3170 ds3/e3 single - chip transceiver 204 of 230 capture - dr. data may be parallel loaded into the test data register selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. on the rising edge of jtclk, the controller goes to the shift - dr state if jtms is low or to the exit1 - dr state if jtms is high. shift - dr. the test data register selected by the current instruction is connected between jtdi and jtdo and shifts data one stage towards its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. exit1 - dr. while in this state, a rising edge on jtclk with jtms high puts the controller in the update - dr state that terminates the scanning process. a rising edge on jtclk with jtms low puts t he controller in the pause -dr state. pause - dr. shifting of the test registers is halted while in this state. all test registers selected by the current instruction retain their previous state. the controller remains in this state while jtms is low. a r ising edge on jtclk with jtms high puts the controller in the exit2 - dr state. exit2 - dr. while in this state, a rising edge on jtclk with jtms high puts the controller in the update - dr state and terminate the scanning process. a rising edge on jtclk with jtms low puts the controller in the shift -dr state. update - dr. a falling edge on jtclk while in the update- dr state latches the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel ou tput due to changes in the shift register. a rising edge on jtclk with jtms low, puts the controller in the run - test - idle state. with jtms high, the controller enters the select -dr- scan state. select -ir - scan. all test registers retain their previous sta te. the instruction register remains unchanged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture - ir state and initiates a scan sequence for the instruction register. jtms high during a rising edge on jtclk pu ts the controller back into the test - logic - reset state. capture - ir. the capture - ir state is used to load the shift register in the instruction register with a fixed value of 001. this value is loaded on the rising edge of jtclk. if jtms is high on the r ising edge of jtclk, the controller enters the exit1 - ir state. if jtms is low on the rising edge of jtclk, the controller enters the shift - ir state. shift - ir. in this state, the shift register in the instruction register is connected between jtdi and jtd o and shifts data one stage for every rising edge of jtclk towards the serial output. the parallel registers, as well as all test registers, remain at their previous states. a rising edge on jtclk with jtms high moves the controller to the exit1 - ir state . a rising edge on jtclk with jtms low keeps the controller in the shift - ir state while moving data one stage through the instruction shift register. exit1 - ir. a rising edge on jtclk with jtms low puts the controller in the pause - ir state. if jtms is hi gh on the rising edge of jtclk, the controller enters the update - ir state and terminate the scanning process. pause - ir. shifting of the instruction register is halted temporarily. with jtms high, a rising edge on jtclk puts the controller in the exit2 - ir state. the controller remains in the pause - ir state if jtms is low during a rising edge on jtclk. exit2 - ir. a rising edge on jtclk with jtms high put the controller in the update - ir state. the controller loops back to the shift - ir state if jtms is low during a rising edge of jtclk in this state. update - ir. the instruction shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becom es the current instruction. a rising edge on jtclk with jtms low, puts the controller in the run - test - idle state. with jtms high, the controller enters the select -dr- scan state.
ds3170 ds3/e3 single - chip transceiver 205 of 230 13.3 jtag instruction register and instructions the instruction register contai ns a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift - ir state, the instruction shift register is connected between jtdi and jtdo. while in the shift - ir state, a rising edge on jtclk with jtms low shifts data one stage toward the serial output at jtdo. a rising edge on jtclk in the exit1 - ir state or the exit2- ir state with jtms high moves the controller to the update - ir state. the falling edge of that same jtclk latches the data in the ins truction shift register to the instruction parallel output. instructions supported by the device and their respective operational binary codes are shown in table 13-1 . table 13- 1 . jtag instruction codes instructions selected register instruction codes extest boundary scan 000 idcode device identification 001 sample/preload boundary scan 010 clamp bypass 011 highz bypass 100 ---- bypass 101 ---- bypass 1 10 bypass bypass 111 sample/preload. this is a mandatory instruction for the ieee 1149.1 specification. this instruction supports two functions. the digital i/os of the device can be sampled at the boundary scan register without interfering with the nor mal operation of the device and the boundary scan register can be pre - loaded for the extest instruction. the positive edge of jtclk in the capture - dr state samples all digital input pins into the boundary scan register. the boundary scan register is connec ted between jtdi and jtdo. the data on jtdi pin is clocked into the boundary scan register and the data captured in the capture - dr state is shifted out the tdo pin in the shift -dr state. extest. this is a mandatory instruction for the ieee 1149.1 specifica tion. this instruction allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled by the update - ir state, the parallel outputs of all digital output pi ns are driven according to the values in the boundary scan registers on the positive edge of jtclk. the boundary scan register is connected between jtdi and jtdo. the positive edge of jtclk in the capture - dr state samples all digital input pins into the bo undary scan register. the negative edge of jtclk in the update - dr state causes all of the digital output pins to be driven according to the values in the boundary scan registers that have been shifted in during the shift - dr state. the outputs are returned to their normal mode or hiz mode at the positive edge of jtclk during the update - ir state when an instruction other than extest or clamp is activated. bypass. this is a mandatory instruction for the ieee 1149.1 specification. when the bypass instruction i s latched into the parallel instruction register, jtdi connects to jtdo through the 1 - bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation. this mode can be used to bypass one or more chips in a s ystem with multiple chips that have their jtag scan chain connected in series. the chips not in bypass can then be tested with the normal jtag modes. idcode. this is a mandatory instruction for the ieee 1149.1 specification. when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code is loaded into the identification register on the rising edge of jtclk following entry into the capture - dr state. shift - dr can be u sed to shift the identification code out serially through jtdo. during test - logic - reset, the identification code is forced into the instruction register?s parallel output. highz. all digital outputs are placed into a high - impedance state. the bypass regis ter is connected between jtdi and jtdo. the outputs are put into the hiz mode when the hiz instruction is loaded in the update - ir state and on the positive edge of jtclk. the outputs are returned to their normal mode or driven from the boundary scan regist er at the positive edge of jtclk during the update - ir state when an instruction other than hiz is activated.
ds3170 ds3/e3 single - chip transceiver 206 of 230 clamp. all digital output pins output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs do not change during the clamp instruction. if the previous instruction was not extest, the outputs will be driven according to the values in the boundary scan register at the positive edge of jtclk in the update - ir state. the typical use of this i nstruction is in a system that has the jtag scan chain of multiple chips connected in series, and all of the chips have their outputs initialized using the extest mode. then some of the chips are left initialized using the clamp mode and others have their io controlled using the extest mode. this reduces the size of the scan chain during the partial testing of the system. 13.4 jtag id codes table 13- 2 . jtag id codes device revision id[31:28] device code id[27:12] m anufacturer?s code id[11:1] required id[0] ds3170 consult factory 0000000001001111 00010100001 1
ds3170 ds3/e3 single - chip transceiver 207 of 230 13.5 jtag functional timing this functional timing for the jtag circuits shows: ? the jtag controller starting from reset state ? shifting out the first 4 lsb bits o f the idcode ? shifting in the bypass instruction (111) while shifting out the mandatory x01 pattern ? shifting the tdi pin to the tdo pin through the bypass shift register ? an asynchronous reset occurs while shifting figure 13- 3 . jtag functional timing jtclk jtrst jtms jtdi jtdo (state) reset x run test idle select dr scan capture dr shift dr exit1 dr update dr select dr scan select ir scan capture ir shift ir exit1 ir update ir select dr scan capture dr shift dr test logic idle (inst) idcode bypass idcode x x x x x output pin output pin level change if in "extest" instruction mode 13.6 io pins all input, output, and inout pins are inout pins in jtag mode.
ds3170 ds3/e3 single - chip transceiver 208 of 230 14 pin configurations table 14- 1 . ds3170 pin assignments for 100 - ba ll csbga (sorted by signal name) signal ball signal ball signal ball signal ball a[0] k5 d[7] k8 roh b6 txp e1 a[1] j2 d[8] j8 rohclk c9 txp e2 a[2] k2 d[9] g6 rohsof f8 width h2 a[3] h3 gpio[1] e8 rpos f10 wr c2 a[4] j3 gpio[2] e7 rser c6 unused1 d6 a[5] k3 gpio[3] f7 rsofo b8 vdd b1 a[6] h4 gpio[4] g7 rst e6 vdd d1 a[7] j4 gpio[5] f6 rxn a3 vdd k4 a[8] h5 gpio[6] g5 rxp a4 vdd k10 ale g4 gpio[7] d3 spi c3 vdd d10 unused2 g2 gpio[8] d4 tclki c10 vdd a7 cs a1 hiz b4 tclko b9 vdd_clad g3 d[0] j5 int d8 test f5 vdd_ja e3 d[1] k9 jtclk a5 tlclk b7 vdd_rx c5 d[10] j9 jtdi c4 tneg d9 vdd_tx f4 d[11] j10 jtdo d5 toh c7 vss c1 d[12] h8 jtms b3 tohclk d7 vss k1 d[13] h9 jtrst e5 tohen e10 vss k6 d[14] h10 mode f3 tohsof g9 vss g10 d[15] g8 rclko a6 tpos e9 vss a10 d[2] j6 rd b2 tser b10 vss a2 d[3] h6 rdy j1 tsofi a9 vss_clad g1 d[4] k7 refclk h1 tsofo c8 vss_ja d2 d[5] j7 rlclk a8 txn f1 vss_rx b5 d[6] h7 rneg f9 txn f2 vss_tx e4
ds3170 ds3/e3 single - chip transceiver 209 of 230 table 14- 2 . ds3170 pin assignments for 100 - ball csbga (sorted by ball #) ball signal ball signal ball signal ball signal a1 cs c6 rser f1 txn h6 d[3] a2 vss c7 toh f2 txn h7 d[6] a3 rxn c8 tsofo f3 mode h8 d[12] a4 rxp c9 rohclk f4 vdd_tx h9 d[13] a5 jtclk c10 t clki f5 test h10 d[14] a6 rclko d1 vdd f6 gpio[5] j1 rdy a7 vdd d2 vss_ja f7 gpio[3] j2 a[1] a8 rlclk d3 gpio[7] f8 rohsof j3 a[4] a9 tsofi d4 gpio[8] f9 rneg j4 a[7] a10 vss d5 jtdo f10 rpos j5 d[0] b1 vdd d6 unused1 g1 vss_clad j6 d[2] b2 rd d7 tohclk g2 unused2 j7 d[5] b3 jtms d8 int g3 vdd_clad j8 d[8] b4 hiz d9 tneg g4 ale j9 d[10] b5 vss_rx d10 vdd g5 gpio[6] j10 d[11] b6 roh e1 txp g6 d[9] k1 vss b7 tlclk e2 txp g7 gpio[4] k2 a[2] b8 rsofo e3 vdd_ja g8 d[15] k3 a[5] b9 tclko e4 vss_tx g 9 tohsof k4 vdd b10 tser e5 jtrst g10 vss k5 a[0] c1 vss e6 rst h1 refclk k6 vss c2 wr e7 gpio[2] h2 width k7 d[4] c3 spi e8 gpio[1] h3 a[3] k8 d[7] c4 jtdi e9 tpos h4 a[6] k9 d[1] c5 vdd_rx e10 tohen h5 a[8] k10 vdd
ds3170 ds3/e3 single - chip transceiver 210 of 230 figure 14- 1 . ds3170 pin assignments ?100- ball csbga (top view) 1 2 3 4 5 6 7 8 9 10 a cs_n vss rxn rxp jtclk rclko vdd rlclk tsofi vss b vdd rd_n jtms hiz_n vss_rx roh tlclk rsofo tclko tser c vss wr_n spi jtdi vdd_rx rser toh tso fo rohclk tclki d vdd vss_ja gpio[7] gpio[8] jtdo unused1 tohclk int_n tneg vdd e txp txp vdd_ja vss_tx jtrst_n rst_n gpio[2] gpio[1] tpos tohen f txn txn mode vdd_tx test_n gpio[5] gpio[3] rohsof rneg rpos g vss_clad unused2 vdd_clad ale gpio[6] d[9] gpio[4] d[15] tohsof vss h refclk width a[3] a[6] a[8] d[3] d[6] d[12] d[13] d[14] j rdy_n a[1] a[4] a[7] d[0] d[2] d[5] d[8] d[10] d[11] k vss a[2] a[5] vdd a[0] vss d[4] d[7] d[1] vdd
ds3170 ds3/e3 single - chip transceiver 211 of 230 15 dc electrical charac teristics absolute maximum ratings volta ge range on any input, bidirectional or open drain output lead with respect to v ss ?????????????????????????????.. - 0.3v to +5.5v supply voltage range (v dd ) with respect to v ss ..?????????????????????? - 0.3v to +3.63v ambient operating temperature range????? ?????????????????????.. - 40c to +85c junction operating temperature range?????????????????????????? - 40c to +125c storage temperature range??????????????????????????????... - 55c to +125c soldering t emperature (reflow) l ead(pb) - free ........................................................................................................................................ +260 c c ontaining lead(pb) ............................................................................................................................... +240 c these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation sect ions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can af fect reliability. ambient operating temperature range is assuming the device is mounted on a jedec standard test board in a convect ion cooled jedec test enclosure. note: the typical values listed below are not production tested. table 15- 1 . recommended dc operating conditions (v dd = 3.3v 5%, t j = - 40c to +85c.) parameter symbol condi tions min typ max units logic 1 v ih 2.4 5.5 v logic 0 v il - 0.3 +0.8 v supply (v dd ) 5% v dd 3.135 3.300 3.465 v table 15- 2 . dc electrical characteristics (t j = - 40c to +85c.) parameter symbol condit ions min typ max units supply current (v dd = 3.465v) i dd (notes 1, 2) 120 145 ma power - down current (all disable bits set) i ddd (note 2) 18 25 ma lead capacitance c io 7 pf input leakage i il -10 +10 a input leakage (input pins with internal pul lup resistors) i ilp -350 +10 a output leakage (when high impedance ) i lo -10 +10 a output voltage (i oh = - 4.0ma) v oh 4ma outputs, v dd = 3.135 2.4 v output voltage (i ol = 4.0ma) v ol 4ma outputs, v dd = 3.135 0.4 v output voltage (i oh = - 6.0m a) v oh 6ma outputs, v dd = 3.135 2.4 v output voltage (i ol = 6.0ma) v ol 6ma outputs, v dd = 3.135 0.4 v note 1: mode ds3 line rate, all outputs enabled. note 2: all outputs loaded with rated capacitance; all inputs between v dd and v ss ; inputs with p ullups connected to v dd .
ds3170 ds3/e3 single - chip transceiver 212 of 230 table 15- 3 . output pin drive pin name type drive strength (ma) tlclk o 6 tpos /tdat o 6 tneg o 6 txp o n/a (analog) txn o n/a (analog) tohclk o 4 tohsof o 4 roh o 4 rohclk o 4 rohsof o 4 tclko/tgclk o 6 tsofo/tden o 6 rser o 6 rclkon/rgclk o 6 rsofo/rden o 6 d[15:0] io 4 rdy oz 6 int oz 4 gpio[7:0] io 4 jtdo oz 4
ds3170 ds3/e3 single - chip transceiver 213 of 230 16 ac timing characteri stics there are several common ac characteristic definitions. these generic d efinitions are shown in figure 16-1 , figure 16-2 , figure 16-3 , and figure 16-4 . definitions that are specific to a given interface are shown in that interface?s subsection. figure 16- 1 . clock period and duty cycle definitions clock t1 t2 t2 figure 16- 2 . rise time, fall time, and jitter definitions clock t1 t4 t3 t3 t4/2 figure 16- 3 . hold, setup, and delay definitions (rising clock edge) clock signal t5 t6 signal t7
ds3170 ds3/e3 single - chip transceiver 214 of 230 figure 16- 4 . hold, setup, and delay definitions (falling clock edge) clock signal t5 t6 signal t7 figure 16- 5 . to/from hi z delay definitions (rising clock edge) clock signal t8 t9 figure 16- 6 . t o/from hi z delay definitions (falling clock edge) clock signal t8 t9
ds3170 ds3/e3 single - chip transceiver 215 of 230 16.1 framer data path ac characteristics all ac timing characteristics are specified with a 25 pf capacitive load on all output pins, v ih = 2.4v and v il = 0.8v. the voltage thresho ld for all timing measurements is vdd/2. the generic timing definitions shown in in figure 16-1 , figure 16-2 , f igure 16-3 , and figure 16-4 apply to this interface . table 16- 1 . framer interface timing (v dd = 3.3v 5%, t j = - 40c to +125c.) parameter symbo l conditions min typ max units clk frequency f1(1/t1) (note 1) 52 mhz clk clock duty cycle (t2/t1) t2/t1 (note 2) 40 50 60 % clk rise or fall times (20% to 80%) t3 (note 2) 4 ns din to clk setup time t5 (note 3) 4 ns clk to din hold time t6 (not e 3) 0 ns clk to dout delay t7 (note 4) 2 10 ns (note 5) 2 8 ns note 1: any mode , tclki, rlclk input clocks. note 2: any mode , tclki, rlclk input clocks. note 3: rlclk clock input to rpos/rdat, rneg/rlcv inputs. note 4: tclki, rlclk clock inpu ts to tpos/tdat, tneg outputs. note 5: tlclkn, tclko, rclko clock outputs to tpos/tdat, tneg outputs. table 16- 2 . system port interface timing (v dd = 3.3v 5%, t j = - 40c to +125c.) parameter symbol condit ions min typ max units clk frequency f1(1/t1) (note 1) 52 mhz clk clock duty cycle (t2/t1) t2/t1 (note 2) 40 50 60 % clk rise or fall times (20% to 80%) t3 (note 2) 4 ns din to clk setup time t5 (note 3) 3 ns (note 4) 7 ns clk to din hold t ime t6 (note 3) 1 ns (note 4) 1 ns clk to dout delay t7 (note 5) 2 10 ns (note 6) 2 8 ns note 1: any mode , tclki, rlclk input clocks. note 2: any mode , tclki, rlclk input clocks. note 3: tclki, rlclk clock inputs to tsofi, tser inputs. no te 4: tclko, rclko clock outputs to tsofi, tser inputs. note 5: tclki, rlclk clock input to tsofo/tden, rser, rsofo/rden outputs. note 6: tclko, rclko clock output to tsofo/tden, rser, rsofo/rden outputs.
ds3170 ds3/e3 single - chip transceiver 216 of 230 table 16- 3 . misc timing (v dd = 3.3v 5%, t j = - 40c to +125c.) parameter symbol conditions min typ max units asynchronous input high, low time t1 - t2, t2 (note 1) 500 ns asynchronous input rise, fall time t3 (note 1) 10 ns note 1: tmei (gpio), pmu ( gpio), 8krefi (gpio) and rst inputs . 16.2 overhead port ac characteristics all ac timing characteristics are specified with a 25 pf capacitive load on all output pins, v ih = 2.4v and v il = 0.8. the voltage threshold for all timing measurements is vdd/2. the generic timing definitions shown in figure 16-1 , figure 16-2 , figure 16-3 , and figure 16-4 apply to this interface . table 16- 4 . overhead port timing (v dd = 3.3v 5%, t j = -40 c to +125 c.) parameter symbol conditions min typ max units clk period t1 (note 1) 500 ns clk clock high and low time t1 - t2, t2 (note 1) 200 ns din to clk setup time t5 (note 2) 20 ns clk to din hold time t6 (note 2) 20 ns clk to dout delay t7 (note 3) -20 20 ns note 1: tohclk, rohclk output clocks. note 2: tohclk cl ock falling edge outputs to toh, tohen inputs. note 3: tohclk, rohclk clock falling edge outputs to tohsof, roh, rohsof outputs.
ds3170 ds3/e3 single - chip transceiver 217 of 230 16.3 micro interface ac characteristics 16.3.1 spi bus mode table 16- 5 . spi bus mode tim ing symbol (1) characteristic (2) symbol min max units operating frequency slave f bus(s) 10 mhz t1 cycle time: slave t cyc(s) 100 ? ns t2 enable lead time t lead(s) 15 ? ns t3 enable lag time t lag(s) 15 ? ns t4 clock (clk) high time slave t clkh(s) 50 ? ns t5 clock (clk) low time slave t clkl(s) 50 ? ns t6 data setup time (inputs) slave t su(s) 5 ? ns t7 data hold time (inputs) slave t h(s) 15 ? ns t8 disable time, slave (3) t dis(s) ? 25 ns t9 data valid time, after enable edge slave (4) t v(s) ? 40 ns t10 data hold time, outputs, after enable edge slave t hd(s) 5 ? ns note 1: symbols refer to dimensions in the following figure. note 2: 100 pf load on all spi pins. note 3: hold time to high - impedance state. note 4: with 100 pf on all spi pins.
ds3170 ds3/e3 single - chip transceiver 218 of 230 fi gure 16- 7 . spi interface timing diagram note: 1. clock edge reference to data controlled by cpha and cpol settings. refer to functional timing diagrams. 2. not defined, but usually msb of character just received. cs input spi_sclk spi_sclk 1 mosi input miso output msb bits 13 - 0 slave msb bits 6-1 note 2 bit 14 t1 t4 t5 t2 t3 slave lsb t8 t6 t7 t9 t10
ds3170 ds3/e3 single - chip transceiver 219 of 230 16.3.2 parallel bus mode the ac characteristics for the external bus interface in parallel mode. this table references figure 16-8 and figure 16-9 . table 16- 6 . micro interface timing (v dd = 3.3v 5%, tj = - 40c to 125c.) signal name(s) symbol description min typ max units note s a[n:0] t1a setup time to rd , wr , ds active 10 ns 1 ale t1b setup time to rd , wr , ds active 10 ns 1, 2 a[n:0] t2 setup time to ale inactive 2 ns 1, 2 a[n:0] t3 hold time from ale inactive 2 ns 1, 2 ale t4 pulse width 5 ns 1, 2 a[n:0], ale t5 hold time from rd , wr , ds inactive 0 ns 1 cs , r/ w t6 setup time to rd , wr active 0 ns 1 d[15:0] t8 output delay time from rd , ds active 30 ns 1 rd , wr , ds t9a pulse width if not using rdy handshake 35 ns 1, 4 rd , wr , ds t9b delay from rdy 15 ns 1 d[15:0] t10 output deassert delay time from rd , ds inactive 2 10 ns 1, 3 cs , r/ w t12 hold time from rd , wr , ds inactive 0 ns 1 d[15:0] t13 input setup time to wr , ds inactive 10 ns 1 d[15:0] t14 input hold time from wr , ds inactive 5 ns 1 rdy t15 delay time from rd , wr , ds active 5 ns 1 rdy t16 delay time from rd , wr , ds inactive 0 ns 1 rdy t17 enable delay time from cs active 18 ns 1 rdy t18 disable delay time from cs inactive 12 ns 1 rdy t19 ending high pulse width 1 ns 1 r/ w t20 setup time to ds active 2 ns 1 r/ w t21 hold time to ds inactive 2 ns 1 note 1: the input/output timing reference level for all signals is vdd/2. transition time (80%/20%) on rd , wr, and cs inputs is 5ns (max). note 2: multiplexed mode tim ing only. note 3: d[15:0] output valid until not driven. note 4: timing required if not using rdy handshake.
ds3170 ds3/e3 single - chip transceiver 220 of 230 figure 16- 8 . micro interface nonmultiplexed read/write cycle d[15 :0] rdy t8 t10 cs t6 t12 rd, wr, ds t9a a[10:0] t5 t1a d[15:0] t13 t14 t15 t16 t17 t18 t19 r/ w t20 t21 t9b
ds3170 ds3/e3 single - chip transceiver 221 of 230 figur e 16- 9 . micro interface multiplexed read cycle d[15:0] rdy t8 t10 cs t6 t12 rd, wr, ds t9a d[15:0] t13 t14 t15 t16 t17 t18 t19 r/ w t20 t21 a[10:0] t1a ale t2 t3 t4 t1b t9b t5
ds3170 ds3/e3 single - chip transceiver 222 of 230 16.4 clad jitter characteristics parameter min typ max units intrinsic jitter (ui p - p ) 0.04 ui p - p intrinsic jitter (ui rms ) 0.01 ui rms peak jitter transfer 1.75 db 16.5 liu interface ac characteristics 16.5.1 waveform templates table 16- 7 . ds3 waveform template time (in unit intervals) normalized amplitude equation upper curve - 0.85 t - 0.68 0.03 - 0.68 t +0.36 0.5 {1 + sin[( / 2)(1 + t / 0.34)]} + 0.03 0.36 t 1.4 0.08 + 0.407e - 1.84(t - 0.36) lower curve - 0.85 t - 0.36 - 0.03 - 0.36 t +0.36 0.5 {1 + sin[( / 2)(1 + t / 0.18)]} - 0.03 0.36 t 1.4 - 0.03 governing specifi cations: ansi t1.102 and bellcore gr - 499 . table 16- 8 . ds3 waveform test parameters and limits parameter specification rate 44.736mbps ( 20ppm) line code b3zs transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the end of 0 to 450ft of coaxial cable test termination 75 ? ( 1%) resistive pulse amplitude between 0.36v and 0.85v pulse shape an isolated pulse (preceded by two zeros and followed by one or more zeros) falls wit hin the curves listed in figure 16 - 11 . unframed all - ones power level at 22.368mhz between - 1.8dbm and +5.7dbm unframed all - ones power level at 44.736mhz at least 20db less than the power measured at 22.368mhz pulse imbalance of isolated pulses ratio of positive and negative pulses must be between 0.90 and 1.10.
ds3170 ds3/e3 single-chip transceiver 223 of 230 figure 16-10. ds3 pulse mask template table 16-9. e3 waveform test parameters and limits parameter specification rate 34.368mbps ( ? 20ppm) line code hdb3 transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the transmitter test termination 75 ? ( ? 1%) resistive pulse amplitude 1.0v (nominal) pulse shape an isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the template shown in figure 16-11 . ratio of the amplitudes of positive and negative pulses at the center of the pulse interval 0.95 to 1.05 ratio of the widths of positive and negative pulses at the nominal half amplitude 0.95 to 1.05
ds3170 ds3/e3 single - chip transceiver 224 of 230 figure 16- 11 . e3 waveform template 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 time (ns) g.703 e3 template output level (v) 29.1 24.5 12.1 8.65 17
ds3170 ds3/e3 single - chip transceiver 225 of 230 16.5.2 liu input/output characteristics table 16- 10 . receiver input characteristics ? ds3 mode (v dd = 3.3v 5%, t a = - 40c to +85c.) parameter min typ max units receive sensitivity (length of cable) 900 1200 ft s ignal - to - noise ratio, interfering signal test (notes 1, 2) 10 input pulse amplitude, rmon = 0 (notes 2, 3) 1000 mvpk input pulse amplitude, rmon = 1 (note 2, 3) 200 mvpk analog los declare, rmon = 0 (note 4) -24 db analog los clear, rmon = 0 ( note 4) -17 db analog los declare, rmon = 1 (note 4) -38 db analog los clear, rmon = 1 (note 4) -29 db intrinsic jitter generation (note 4) 0.03 ui p - p table 16- 11 . receiver input characteristics ?e 3 mode (v dd = 3.3v 5%, t a = - 40c to +85c.) parameter min typ max units receive sensitivity (length of cable) 900 1200 ft signal - to - noise ratio, interfering signal test (notes 1, 2) 12 input pulse amplitude, rmon = 0 (notes 2, 3) 1300 mvpk inp ut pulse amplitude, rmon = 1 (notes 2, 3) 260 mvpk analog los declare, rmon = 0 (note 4) -24 db analog los clear, rmon = 0 (note 4) -17 db analog los declare, rmon = 1 (note 4) -38 db analog los clear, rmon = 1 (note 4) -29 db intrinsic jitt er generation (note 4) 0.03 ui p - p note 1: an interfering signal (2 15 ? 1 prbs for ds3, 2 23 ? 1 prbs for e3, b3zs/hdb3 encoded, compliant waveshape, nominal bit rate) is added to the wanted signal. the combined signal is passed through 0 to 900ft of coa xial cable and presented to the ds3154 receiver. this spec indicates the lowest signal -to - noise ratio that results in a bit error ratio < 10 -9 . note 2: not tested during production test. note 3: measured on the line side (i.e., the bnc connector side) of the 1:2 receive transformer ( figure 2 - 1 ). during measurement, incoming data traffic is unframed 2 15 ? 1 prbs for ds3 and unframed 2 23 ? 1 prbs for e3. note 4: with respect to nominal 800mvpk signal for d s3 and nominal 1000mvpk signal for e3.
ds3170 ds3/e3 single - chip transceiver 226 of 230 table 16- 12 . transmitter output characteristics ? ds3 modes (v dd = 3.3v 5%, t a = - 40c to +85c.) parameter min typ max units ds3 output pulse amplitude, tlbo = 0 (not e 1) 700 800 900 mvpk ds3 output pulse amplitude, tlbo = 1 (note 1) 520 700 800 mvpk ratio of positive and negative pulse - peak amplitudes 0.9 1.1 ds3 unframed all - ones power level at 22.368mhz, 3khz bandwidth - 1.8 +5.7 dbm ds3 unframed all - ones pow er level at 44.736mhz vs. power level at 22.368mhz, 3khz bandwidth -20 db intrinsic jitter generation (note 2) 0.02 0.05 ui p - p table 16- 13 . transmitter output characteristics ? e3 mode (v dd = 3.3v 5%, t a = - 40c to +85c.) parameter min typ max units output pulse amplitude (note 1) 900 1000 1100 mvpk pulse width 14.55 ns ratio of positive and negative pulse amplitudes (at centers of pulses) 0.95 1.05 ratio of positive and negative pulse widths (a t nominal half amplitude) 0.95 1.05 intrinsic jitter generation (note 2) 0.02 0.05 ui p - p note 1: measured on the line side (i.e., the bnc connector side) of the 2:1 transmit transformer ( figure 2 -1 ). note 2: measured with jitter - free clock applied to tclk and a bandpass jitter filter with 10hz and 800khz cutoff frequencies. not tested during production test.
ds3170 ds3/e3 single - chip transceiver 227 of 230 16.6 jtag interface ac characteristics all ac timing characteristics are specified with a 50 pf capacitive load on jtdo pin and 25 pf capacitive load on all other digital output pins, v ih = 2.4v and v il = 0.8. the voltage threshold for all timing measurements is vdd/2. the voltage threshold for all timing measurements is vdd/2. the generic timing de finitions shown in figure 16-1 , figure 16-2 , figure 16-3 , and figure 16-4 apply to this interface . table 16- 14 . jtag interface timing (v dd = 3.3v 5%, t j = - 40c to +125c.) signal name(s) symbol description min typ max units notes jtclk f1 clock frequen cy (1/t1) 0 10 mhz jtclk t2 clock high or low period 20 ns jtclk t3 rise/fall times 5 ns jtms and jtdi t5 hold time from jtclk rising edge 10 ns jtms and jtdi t6 setup time to jtclk rising edge 10 ns jtdo t7 delay from jtclk falling edge 0 20 ns jtdo t8 delay out of hi z from jtclk falling edge 0 20 ns jtdo t9 delay to hi z from jtclk falling edge 0 20 ns any digital output t7 delay from jtclk falling edge 0 20 ns 1 any digital output t7 delay from jtclk rising edge 0 20 ns 2 any digital output t8 delay out of hi z from jtclk falling edge 0 20 ns 1 any digital output t9 delay into hi z from jtclk falling edge 0 20 ns 1 any digital output t8 delay out of hi z from jtclk rising edge 0 20 ns 2, 3 any digital output t9 dela y into hi z from jtclk rising edge 0 20 ns 2, 3 note 1: change during update - dr state. note 2: change during update - ir state to or from extest mode. note 3: change during update - ir state to or from hiz mode.
ds3170 ds3/e3 single - chip transceiver 228 of 230 17 package information for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffi x character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 100 csbga x100+4 21-0352 90-0292
ds3170 ds3/e3 single - chip transceiver 229 of 230 18 thermal information table 18- 1 . thermal information parameter value target ambient temperature range - 40c to +85c die junction temperature range - 40c to +125c theta - ja, still air (note 1) 38.5c/w note 1: theta - ja is based on the package mounted on a four - layer jedec board and measured in a jedec test chamber.
ds3170 ds3/e3 single - chip transceiver 230 of 230 ma xim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 20 11 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. 19 revision history revision number revision date description pages changed 0 101404 new product release. ? 1 050506 removed lqfp package from data sheet. 1, 25, 26, 27, 208, 209, 212, 214, 215 2 3 / 11 add ed l ead (pb)- free device s to the o rdering i nformation 1 section 4.1 global features corrected. from: on - chip cloc k rate adapter incorporates two separate internal plls to generate the necessary ds3 or e3 clock used internally from an input clock reference (ds3, e3, 51.84 mhz, 77.76 mhz, or 19.44 mhz) and to provide an output reference clock for external usage to: on - chip clock rate adapter incorporates two separate internal plls to generate the necessary ds3 or e3 clock used internally from an input clock reference (ds3, e3, 51.84 mhz, 77.76 mhz, or 19.44 mhz) 13 section 10.1.7 interrupt and pin modes. replaced ? float? with ?high impedance? 54 section 15 dc electrical characteristics, absolute maximum ratings. updated soldering t emperature to include pb and pb free 211 table 15 - 2. dc electrical characteristics. replace d ?hi - z? with ?high impedance? 211 no te: to obtain a revision history for the preliminary releases of this document, contact the factory at www.maxim - ic.com/support .


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